Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

Renesas UPA1760G-E1-AT

Name: UPA1760G-E1-AT
Brand: Renesas
SKU: UPA1760G-E1-AT
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: UPA1760G-E1-AT

Manufacturer:: Renesas

Category:: FETs, MOSFETs

Package:: 8-SOIC (0.173", 4.40mm Width)

Datasheet:: UPA1760G-E1-AT.pdf

Description:: MOSFET 2N-CH 30V 8A 8SOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:80,000

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

UPA1760G-E1-AT from Renesas Electronics is a dual N-channel power MOSFET in Power SOP8 package, designed for synchronous rectification and high-efficiency DC/DC converters in notebook computers. It delivers R_DS(on)1 = 26.0 mΩ max at V_GS = 10 V / I_D = 4.0 A, C_iss = 760 pF typ., and supports ±8.0 A DC drain current with built-in gate-source ESD protection diodes.

For engineers reviewing the UPA1760G-E1-AT datasheet, UPA1760G-E1-AT pinout, UPA1760G-E1-AT application, or UPA1760G-E1-AT equivalent, key selection criteria include low-voltage gate drive capability (R_DS(on)2 = 36.0 mΩ max at V_GS = 4.5 V), avalanche ruggedness (E_AS = 6.4 mJ), and dual-die thermal coupling in a surface-mount power package.

Technical Context

The UPA1760G-E1-AT integrates two independent N-channel enhancement-mode MOSFETs on a single die within a Power SOP8 thermally enhanced package. Its dual-chip architecture enables synchronous buck converter topologies where one FET serves as high-side switch and the other as low-side synchronous rectifier - sharing common source terminals (pins 1 & 4) and isolated gate/drain connections.

It features gate-to-source Zener clamping (±20 V rating), body diode recovery time t_rr = 30 ns at I_F = 8.0 A, and specified avalanche capability under controlled inductive switching (I_AS = 8 A, E_AS = 6.4 mJ). Channel temperature is rated to 150°C with derated power dissipation above 25°C ambient.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DSS	30 V - Maximum blocking voltage for 5 V–12 V input DC/DC stages
R_DS(on)1	26.0 mΩ max at V_GS = 10 V / I_D = 4.0 A - Enables <1 W conduction loss per FET at 4 A
R_DS(on)2	36.0 mΩ max at V_GS = 4.5 V / I_D = 4.0 A - Supports logic-level gate drive from PWM controllers
C_iss	760 pF typ. at V_DS = 10 V - Limits gate drive power and switching transition speed
Q_G	14 nC typ. - Determines minimum gate driver peak current requirement (~1.4 A for 10 ns rise)
t_r/t_f	140 ns / 30 ns - Fast turn-on but slower fall enables reduced shoot-through risk in synchronous operation
E_AS	6.4 mJ - Withstands single-pulse inductive energy during overcurrent or hard-switching events

Pinout & Package

UPA1760G-E1-AT uses the Power SOP8 (M8E) package: 4.4 mm × 6.0 mm footprint, 1.8 mm max height, with exposed drain pad for thermal conduction. Pin 1 and Pin 4 are Source 1 and Source 2 respectively; Pins 2 and 5 are Gate 1 and Gate 2; Pins 3, 6, 7, 8 are Drain 1 and Drain 2 tied together internally per channel.

Pin/Terminal	Circuit Role	Design Meaning
1	Source 1	Low-side FET source node - connects to output inductor and load ground reference
2	Gate 1	Control terminal for low-side FET - requires gate driver with 14 nC charge capacity
3, 6, 7, 8	Drain 1	Shared drain connection for low-side FET - ties to power ground plane via exposed pad
4	Source 2	High-side FET source node - connects to switching node between input and inductor
5	Gate 2	Control terminal for high-side FET - referenced to floating source (requires level-shifted drive)
3, 6, 7, 8	Drain 2	Shared drain connection for high-side FET - ties to input supply rail (V_IN)

Key Features

Feature	Design Value
Dual N-channel configuration	Enables compact synchronous buck converter layout with shared thermal path and matched R_DS(on) tracking
Built-in G-S protection diode	Zener-clamped gate structure withstands ±20 V transients - eliminates need for external gate protection
Low C_iss / C_oss ratio	C_iss = 760 pF, C_oss = 250 pF - improves efficiency in hard-switched topologies by reducing Miller effect
Fast body diode recovery	t_rr = 30 ns, Q_rr = 20 nC - minimizes reverse recovery losses during synchronous rectification
Avalanche-rated operation	Rated for single-pulse I_AS = 8 A and E_AS = 6.4 mJ - enhances robustness against inductive switching faults

Applications

Notebook DC/DC Converters	USB-C PD Power Stages
Use Scenario: Step-down conversion from 12 V or 19 V adapter input to 1.0–3.3 V core/logic rails in thin-and-light notebooks. IC Role / Device Role / Timing Role: Dual FET operates as synchronous rectifier (low-side) and high-side switch in integrated buck controller IC reference designs. Use Value: R_DS(on)2 ≤ 36 mΩ at 4.5 V gate drive enables >92% efficiency at 4 A load without external gate boosting.	Use Scenario: Secondary-side synchronous rectification in 20–60 W USB-C Power Delivery adapters targeting compact form factors. IC Role / Device Role / Timing Role: Low-side FET handles continuous 5–10 A output current while high-side FET manages input-side switching in hybrid topologies. Use Value: Matched thermal coupling between channels ensures balanced current sharing and prevents localized hot spots during sustained 8 A operation.
Industrial SMPS Modules	Embedded System PMICs
Use Scenario: 24 V input to 5 V/3.3 V regulation in DIN-rail mounted programmable logic controllers and sensor interface modules. IC Role / Device Role / Timing Role: Dual-FET replaces discrete high/low-side pairs - simplifies layout and reduces BOM count in space-constrained PCBs. Use Value: 150°C channel rating and 2.0 W total package dissipation support operation in sealed enclosures up to 70°C ambient.	Use Scenario: Integrated power management for ARM-based industrial gateways requiring multiple regulated rails with tight transient response. IC Role / Device Role / Timing Role: Functions as main buck stage switch pair in multi-phase or interleaved configurations driven by external PWM signals. Use Value: 30 V V_DSS and 8 A pulse rating accommodate 24 V input surges and 100 µs overload transients without derating.

Notebook DC/DC Converters

USB-C PD Power Stages

Use Scenario: Step-down conversion from 12 V or 19 V adapter input to 1.0–3.3 V core/logic rails in thin-and-light notebooks.

IC Role / Device Role / Timing Role: Dual FET operates as synchronous rectifier (low-side) and high-side switch in integrated buck controller IC reference designs.

Use Value: R_DS(on)2 ≤ 36 mΩ at 4.5 V gate drive enables >92% efficiency at 4 A load without external gate boosting.

Use Scenario: Secondary-side synchronous rectification in 20–60 W USB-C Power Delivery adapters targeting compact form factors.

IC Role / Device Role / Timing Role: Low-side FET handles continuous 5–10 A output current while high-side FET manages input-side switching in hybrid topologies.

Use Value: Matched thermal coupling between channels ensures balanced current sharing and prevents localized hot spots during sustained 8 A operation.

Industrial SMPS Modules

Embedded System PMICs

Use Scenario: 24 V input to 5 V/3.3 V regulation in DIN-rail mounted programmable logic controllers and sensor interface modules.

IC Role / Device Role / Timing Role: Dual-FET replaces discrete high/low-side pairs - simplifies layout and reduces BOM count in space-constrained PCBs.

Use Value: 150°C channel rating and 2.0 W total package dissipation support operation in sealed enclosures up to 70°C ambient.

Use Scenario: Integrated power management for ARM-based industrial gateways requiring multiple regulated rails with tight transient response.

IC Role / Device Role / Timing Role: Functions as main buck stage switch pair in multi-phase or interleaved configurations driven by external PWM signals.

Use Value: 30 V V_DSS and 8 A pulse rating accommodate 24 V input surges and 100 µs overload transients without derating.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual N-channel power MOSFET applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si7850DP-T1-GE3	Single-channel 30 V / 11.5 mΩ (V_GS = 10 V); no integrated dual die	Requires two separate devices and additional layout area; lacks matched thermal coupling	Preferred when higher R_DS(on) tolerance allows split-device design and board space permits
DMN3029LSD-13	Dual N-channel, 30 V, R_DS(on) = 29 mΩ / 33 mΩ at V_GS = 10 V; SO-8 package, no exposed pad	Lower thermal performance (no exposed drain pad); higher C_iss = 920 pF limits switching frequency	Suitable for cost-sensitive, lower-power (<5 A) applications where thermal margin is less critical

Compared with Si7850DP-T1-GE3 and DMN3029LSD-13, the UPA1760G-E1-AT provides superior thermal coupling, lower gate charge (14 nC vs. ≥18 nC), and integrated avalanche energy rating - making it optimal for high-density, high-reliability notebook and industrial DC/DC designs.

Availability

UPA1760G-E1-AT is available at Aetrix Electronics and suitable for notebook DC/DC converters, USB-C PD power stages, and industrial SMPS modules requiring stable component supply and long-term lifecycle support.

Supply support for UPA1760G-E1-AT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and consumer markets.

The UPA1760G-E1-AT belongs to Renesas' legacy µPA series of power MOSFETs engineered specifically for high-efficiency, space-constrained DC/DC conversion in portable computing and embedded systems.

FAQ

What is the maximum continuous drain current rating for UPA1760G-E1-AT?

The UPA1760G-E1-AT is rated for ±8.0 A DC drain current per channel at T_A = 25°C on a 2000 mm² ceramic substrate. Derating applies above 25°C ambient - e.g., ~5.5 A at 70°C ambient. This rating assumes proper PCB copper area and thermal vias under the exposed drain pad to maintain channel temperature ≤150°C.

Does UPA1760G-E1-AT support 4.5 V gate drive for both channels?

Yes - UPA1760G-E1-AT specifies R_DS(on)2 = 36.0 mΩ max at V_GS = 4.5 V / I_D = 4.0 A for each channel, confirming full logic-level compatibility. The gate threshold voltage V_GS(off) ranges from 1.5 V to 2.5 V, ensuring reliable turn-on with standard 4.5 V PWM drivers without level-shifting for the low-side channel.

How is the thermal performance of UPA1760G-E1-AT validated?

Thermal performance of UPA1760G-E1-AT is defined by its transient thermal resistance r_th(t) = 73.5°C/W (ch-to-ambient, single pulse), measured on a 2000 mm² × 1.6 mm ceramic substrate. The Power SOP8 package includes an exposed drain pad that must be soldered to a large copper pour with ≥6 thermal vias for optimal heat transfer - enabling 2.0 W total dissipation across both FETs.

Can UPA1760G-E1-AT be used in avalanche mode repeatedly?

No - UPA1760G-E1-AT is rated for single-pulse avalanche only (I_AS = 8 A, E_AS = 6.4 mJ, starting T_ch = 25°C). Repeated avalanche operation is not characterized or guaranteed. Designers must implement overcurrent protection and clamp circuits to avoid repetitive stress, as cumulative energy exposure degrades reliability.

What is the body diode forward voltage of UPA1760G-E1-AT at 8 A?

The body diode forward voltage V_F(S-D) of UPA1760G-E1-AT is 0.86 V typical at I_F = 8.0 A and V_GS = 0 V. This low V_F reduces conduction loss during dead-time conduction in synchronous buck converters, directly improving light-load efficiency compared to discrete Schottky alternatives.

UPA1760G-E1-AT Specifications

Product attributes: Attribute value

Manufacturer:: Renesas

Series:: -

Package/Case:: 8-SOIC (0.173", 4.40mm Width)

Packaging:: Bulk

Product Status:: Obsolete

FET Type:: -

Technology:: MOSFET (Metal Oxide)

Drain to Source Voltage (Vdss):: -

Current - Continuous Drain (Id) @ 25°C:: 8A (Ta)

Drive Voltage (Max Rds On, Min Rds On):: -

Rds On (Max) @ Id, Vgs:: 26mOhm @ 4A, 10V

Vgs(th) (Max) @ Id:: 2.5V @ 1mA

Gate Charge (Qg) (Max) @ Vgs:: -

Vgs (Max):: -

Input Capacitance (Ciss) (Max) @ Vds:: -

FET Feature:: -

Power Dissipation (Max):: -

Operating Temperature:: 150°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-SOP

UPA1760G-E1-AT FAQ

1.How can I place an order for UPA1760G-E1-AT through Aetrix?

Please submit a Request for Quotation (RFQ) for UPA1760G-E1-AT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for UPA1760G-E1-AT reliable?

The price and inventory of UPA1760G-E1-AT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UPA1760G-E1-AT is usually 5 days.

3.What payment methods are accepted for UPA1760G-E1-AT?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UPA1760G-E1-AT transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for UPA1760G-E1-AT?

UPA1760G-E1-AT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your UPA1760G-E1-AT order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for UPA1760G-E1-AT?

For technical support, including UPA1760G-E1-AT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UPA1760G-E1-AT requirements.

6.How does Aetrix verify that UPA1760G-E1-AT is sourced from the original manufacturer or authorized distributors?

All UPA1760G-E1-AT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UPA1760G-E1-AT meets industry standards.

7.What is the process for return or replacement of UPA1760G-E1-AT?

All UPA1760G-E1-AT units undergo pre-shipment inspection (PSI). If there is an issue with UPA1760G-E1-AT, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The UPA1760G-E1-AT part is unused and in its original packaging.

Return procedure for UPA1760G-E1-AT:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…