Renesas UPA1820GR-9JG-E1-A
- Part No.:
- UPA1820GR-9JG-E1-A
- Manufacturer:
- Renesas
- Category:
- FETs, MOSFETs
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
UPA1820GR-9JG-E1-A.pdf
- Description:
- MOSFET N-CH 20V 12A 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:21,000
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
UPA1820GR-9JG-E1-A from Renesas Electronics is a dual N-channel MOSFET in Power TSSOP-8 package, rated for 20 V VDSS, ±12 A DC drain current, and featuring RDS(on) as low as 6.8 mΩ at VGS = 4.5 V. It supports direct 2.5 V gate drive and integrates gate-source ESD protection diodes. It is designed for high-efficiency synchronous rectification and power switching in notebook computer DC/DC converters.
For engineers reviewing the UPA1820GR-9JG-E1-A datasheet, UPA1820GR-9JG-E1-A pinout, UPA1820GR-9JG-E1-A application, or UPA1820GR-9JG-E1-A equivalent, key selection criteria include its dual-channel layout, 2.5 V logic-level drivability, low RDS(on) at sub-4.5 V gate bias, integrated G-S ESD diode, and thermal performance on ceramic substrates.
Technical Context
The UPA1820GR-9JG-E1-A integrates two independent N-channel enhancement-mode MOSFETs in a single Power TSSOP-8 package with shared source terminals per channel (pins 2–3 = Source1, pins 6–7 = Source2). Its gate threshold voltage VGS(off) ranges from 0.5 V to 1.5 V, enabling reliable turn-on with 2.5 V logic. The device exhibits fast switching with td(on) = 18 ns and tf = 52 ns under specified test conditions.
It features a built-in gate-source protection diode per channel but requires external overvoltage protection when subjected to transients exceeding ±12 V VGSS. Its safe operating area (SOA) is defined up to 100 ms pulse width at TA = 25°C on ceramic substrate, with RDS(on) limited conduction boundary dominating at high VDS.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDSS | 20 V - Maximum blocking voltage before avalanche; sets upper limit for input/output rail in buck converter top/bottom switches. |
| RDS(on) @ VGS = 4.5 V | 6.8 mΩ (typ), 8.6 mΩ (max) - Enables <100 mW conduction loss at 6 A DC, critical for thermally constrained notebook power stages. |
| ID(DC) | ±12 A - Continuous current rating per channel; defines maximum steady-state load handling without derating on ceramic substrate. |
| QG | 27 nC - Total gate charge determines driver strength requirement; compatible with standard PWM controller gate drivers. |
| tr/tf | 56 ns / 52 ns - Fast edge rates reduce switching losses in high-frequency (≥300 kHz) DC/DC designs. |
| VGS(th) | 0.5–1.5 V - Low threshold enables full enhancement with 2.5 V logic supply, eliminating level-shifting in compact systems. |
| Ciss | 2020 pF - Input capacitance impacts gate drive loop stability and Miller effect during hard switching. |
Pinout & Package
UPA1820GR-9JG-E1-A is housed in a Power TSSOP-8 package (6.4 mm × 4.4 mm × 1.0 mm max height) with exposed drain pads for thermal enhancement. Pin 1 and Pin 8 are Drain1 and Drain2 respectively; pins 2–3 form Source1, pins 6–7 form Source2; pins 4 and 5 are Gate1 and Gate2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Drain1 | Main current path for Channel 1; electrically connected to exposed pad for thermal conduction to PCB. |
| 2, 3 | Source1 | Reference node for Channel 1; tied to local ground or low-side switch node in synchronous buck configuration. |
| 4 | Gate1 | Control terminal for Channel 1; requires ≤12 V drive; protected by internal G-S diode. |
| 5 | Gate2 | Independent control terminal for Channel 2; enables dual-switching or parallel operation without cross-talk. |
| 6, 7 | Source2 | Reference node for Channel 2; may be tied to Source1 for paralleling or kept separate for isolated half-bridge use. |
| 8 | Drain2 | Main current path for Channel 2; symmetric layout to Pin 1 for balanced thermal distribution. |
Key Features
| Feature | Design Value |
|---|---|
| 2.5 V logic-compatible gate drive | Guarantees full enhancement at VGS = 2.5 V (RDS(on) ≤ 12 mΩ), enabling direct interface with low-voltage microcontrollers and PMICs. |
| Dual N-channel topology in single package | Reduces board space and layout complexity in synchronous rectifier or dual-phase DC/DC applications versus discrete solutions. |
| Built-in gate-source ESD protection diodes | Provides Class 2 HBM ESD robustness (per datasheet note), reducing need for external TVS in non-harsh environments. |
| Low QGD/QG ratio (13 nC / 27 nC) | Minimizes Miller-induced shoot-through risk during hard switching, improving reliability in high-dV/dt applications. |
| Thermally optimized Power TSSOP-8 | Exposed drain pads allow >1.5 W dissipation on 5000 mm² ceramic substrate, supporting compact high-power density designs. |
Applications
| High-Efficiency Notebook DC/DC Converter | Synchronous Buck Regulator for CPU Core Supply |
|---|---|
Use Scenario: Step-down conversion from 12 V or 5 V input to 1.0–1.8 V output delivering up to 25 A to mobile CPU cores. IC Role / Device Role / Timing Role: Dual N-channel MOSFET used as synchronous rectifier (low-side) and active switch (high-side) in single-phase buck stage. Use Value: RDS(on) ≤ 8.8 mΩ at 4.0 V gate drive reduces conduction loss by >30% vs. older 12 V gate-driven MOSFETs, extending battery runtime. | Use Scenario: High-current, high-switching-frequency (500 kHz–1 MHz) point-of-load regulator on ultrabook motherboard. IC Role / Device Role / Timing Role: Configured as dual low-side switches in multiphase interleaved architecture or as redundant channel for fault-tolerant design. Use Value: Matched RDS(on) and QG between channels ensures balanced current sharing and eliminates phase-skew-induced ripple. |
| USB-C PD Power Path Switch | Industrial 24 V DC/DC Intermediate Bus Converter |
Use Scenario: Bidirectional 20 V/3 A power path management between USB-C port and system battery in portable devices. IC Role / Device Role / Timing Role: Used as back-to-back configured N-MOSFET pair to block reverse current and support USB PD 3.0 programmable power supply negotiation. Use Value: 20 V VDSS and 2.5 V drive compatibility enable direct integration with USB PD controller GPIOs without level shifters. | Use Scenario: 24 V input to 5 V/12 V intermediate bus conversion in factory automation I/O modules with space constraints. IC Role / Device Role / Timing Role: Employed as primary-side synchronous rectifier in forward or active-clamp flyback topology. Use Value: Low Ciss (2020 pF) and fast tf (52 ns) minimize switching losses at 300–400 kHz, improving efficiency above 92% at full load. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual N-channel MOSFET switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si7852DP-T1-GE3 | 30 V VDSS, RDS(on) = 9.5 mΩ @ 4.5 V, SO-8 package, no integrated G-S diode. | Higher voltage rating suits 24 V industrial rails; lacks on-chip ESD protection requiring external diodes. | Select when higher blocking voltage or SO-8 footprint compatibility is required; verify external ESD protection. |
| DMN3022LSD-13 | 30 V VDSS, RDS(on) = 12.5 mΩ @ 4.5 V, dual N-channel in SO-8, no G-S diode, QG = 11 nC. | Lower gate charge reduces driver loading but higher RDS(on) increases conduction loss at >5 A. | Prefer for lower-power, high-frequency applications where gate drive strength is limited; not suitable for 12 A DC loads. |
Compared with Si7852DP-T1-GE3 and DMN3022LSD-13, the UPA1820GR-9JG-E1-A offers superior 2.5 V drive capability and integrated ESD protection-critical for space-constrained, low-voltage notebook power stages-while trading off voltage rating and gate charge for lower on-resistance at mid-range gate voltages.
Availability
UPA1820GR-9JG-E1-A is available at Aetrix Electronics and suitable for high-efficiency DC/DC converters, notebook power management systems, and USB-C PD power path switching requiring stable component supply and long-lifecycle support.
Supply support for UPA1820GR-9JG-E1-A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, power, and mixed-signal ICs for automotive, industrial, and consumer applications.
The UPA1820GR-9JG-E1-A belongs to Renesas' legacy µPA series of logic-level power MOSFETs, engineered specifically for high-density, low-voltage power conversion in portable computing and battery-powered systems.
FAQ
What is the maximum continuous drain current rating for UPA1820GR-9JG-E1-A?
The UPA1820GR-9JG-E1-A is rated for ±12 A DC drain current per channel at TA = 25°C when mounted on a 5000 mm² ceramic substrate. This rating assumes proper thermal management; derating is required above 25°C ambient or on FR-4 boards. The device's RDS(on) and SOA curves must be consulted to confirm safe operation under actual board-level thermal conditions for UPA1820GR-9JG-E1-A.
Does UPA1820GR-9JG-E1-A support true 2.5 V gate drive across its full current range?
Yes - the UPA1820GR-9JG-E1-A guarantees RDS(on) ≤ 12 mΩ at VGS = 2.5 V and ID = 6.0 A, confirming full enhancement at 2.5 V logic levels. Its VGS(off) range (0.5–1.5 V) ensures robust turn-on margin. This makes UPA1820GR-9JG-E1-A suitable for direct drive from 2.5 V GPIOs or low-voltage PMIC outputs without level shifting.
What is the purpose of the internal gate-source protection diode in UPA1820GR-9JG-E1-A?
The internal gate-source diode in UPA1820GR-9JG-E1-A provides electrostatic discharge (ESD) protection per the datasheet's Class 2 HBM specification. It clamps transient gate overvoltage but does not replace external protection when sustained overvoltage (>±12 V) or fast transients are expected. Designers must still implement external TVS or RC networks for robust system-level ESD immunity in UPA1820GR-9JG-E1-A applications.
Can UPA1820GR-9JG-E1-A be used in synchronous rectifier configurations?
Yes - UPA1820GR-9JG-E1-A is explicitly designed for synchronous rectification in DC/DC converters. Its low RDS(on), fast switching (tf = 52 ns), and matched dual-channel structure allow efficient replacement of Schottky diodes in buck, boost, and flyback topologies. The body diode VF(S-D) = 0.81 V at 12 A further supports low-loss freewheeling in UPA1820GR-9JG-E1-A-based synchronous rectifiers.
Is UPA1820GR-9JG-E1-A qualified for automotive applications?
No - UPA1820GR-9JG-E1-A is classified as a "Standard" quality grade device per Renesas documentation, intended for computers, office equipment, and consumer electronics. It is not AEC-Q101 qualified and lacks automotive-specific stress testing, failure rate data, or extended temperature support. For automotive use, designers must select Renesas' "High Quality" or AEC-Q101-certified alternatives instead of UPA1820GR-9JG-E1-A.
UPA1820GR-9JG-E1-A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 20 V
- Current - Continuous Drain (Id) @ 25°C:
- 12A (Ta)
- Drive Voltage (Max Rds On, Min Rds On):
- -
- Rds On (Max) @ Id, Vgs:
- 8.6mOhm @ 6A, 4.5V
- Vgs(th) (Max) @ Id:
- 1.5V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 27 nC @ 4 V
- Vgs (Max):
- -
- Input Capacitance (Ciss) (Max) @ Vds:
- 2020 pF @ 10 V
- FET Feature:
- -
- Power Dissipation (Max):
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
UPA1820GR-9JG-E1-A FAQ
1.How can I place an order for UPA1820GR-9JG-E1-A through Aetrix?
Please submit a Request for Quotation (RFQ) for UPA1820GR-9JG-E1-A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UPA1820GR-9JG-E1-A reliable?
The price and inventory of UPA1820GR-9JG-E1-A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UPA1820GR-9JG-E1-A is usually 5 days.
3.What payment methods are accepted for UPA1820GR-9JG-E1-A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UPA1820GR-9JG-E1-A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UPA1820GR-9JG-E1-A?
UPA1820GR-9JG-E1-A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UPA1820GR-9JG-E1-A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UPA1820GR-9JG-E1-A?
For technical support, including UPA1820GR-9JG-E1-A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UPA1820GR-9JG-E1-A requirements.
6.How does Aetrix verify that UPA1820GR-9JG-E1-A is sourced from the original manufacturer or authorized distributors?
All UPA1820GR-9JG-E1-A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UPA1820GR-9JG-E1-A meets industry standards.
7.What is the process for return or replacement of UPA1820GR-9JG-E1-A?
All UPA1820GR-9JG-E1-A units undergo pre-shipment inspection (PSI). If there is an issue with UPA1820GR-9JG-E1-A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UPA1820GR-9JG-E1-A part is unused and in its original packaging.
Return procedure for UPA1820GR-9JG-E1-A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
UPA1820GR-9JG-E1-A Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
