Diodes Incorporated ZVP4105ASTOA
- Part No.:
- ZVP4105ASTOA
- Manufacturer:
- Diodes Incorporated
- Category:
- FETs, MOSFETs
- Package:
- E-Line-3
- Datasheet:
-
ZVP4105ASTOA.pdf
- Description:
- MOSFET P-CH 50V 175MA E-LINE
- Quantity:
- Payment:

- Shipping:

Inventory:9,895
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Product details
Overview
ZVP4105ASTOA from Zetex Semiconductors (now Diodes Incorporated) is a P-channel enhancement-mode vertical DMOS FET rated for -50 V VDS, 10 Ω RDS(on) at VGS = -5 V, and -175 mA continuous drain current. It operates in low-power switching roles such as load switching and level translation in battery-powered instrumentation and portable logic interfaces.
For engineers reviewing the ZVP4105ASTOA datasheet, ZVP4105ASTOA pinout, ZVP4105ASTOA application, or ZVP4105ASTOA equivalent, key selection criteria include verified gate threshold range (-0.8 to -2.0 V), guaranteed RDS(on) ≤10 Ω under pulsed conditions, and TO-92-compatible leadform with confirmed Drain-Gate-Source terminal assignment.
Technical Context
This device uses vertical DMOS construction to achieve stable breakdown voltage and low on-resistance in a through-hole package. Its enhancement-mode operation requires negative gate bias relative to source to conduct, with gate threshold tightly specified between -0.8 V and -2.0 V at -1 mA drain current.
Switching performance is characterized with 50 Ω source impedance and sub-5 ns pulse rise time: turn-on delay is 10 ns, rise time 10 ns, turn-off delay 18 ns, and fall time 25 ns at VDD ≈ -30 V and ID = -270 mA - confirming suitability for medium-speed digital control paths.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | -50 V - maximum blocking voltage before avalanche conduction in reverse-biased drain-source path |
| RDS(on) | 10 Ω @ VGS = -5 V, ID = -100 mA - defines power loss and voltage drop in saturated switch mode |
| ID (cont) | -175 mA @ Tamb = 25°C - continuous DC current handling limited by 625 mW package power dissipation |
| VGS(th) | -0.8 to -2.0 V @ ID = -1 mA - ensures reliable turn-on with standard CMOS/TTL logic-level drive |
| Ciss | 40 pF @ VDS = -25 V, VGS = 0 V - impacts gate drive energy and high-frequency switching efficiency |
| td(off) | 18 ns - determines minimum off-time in PWM-controlled loads operating up to ~5 MHz |
Pinout & Package
Supplied in E-Line TO-92-compatible plastic package with molded leads and standardized footprint. Pin identification follows standard TO-92 orientation: viewed from flat side with leads down, left-to-right pin order is Drain–Gate–Source.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 (Left) | Drain | Main current-carrying terminal; connected to high-side or floating load node |
| Pin 2 (Center) | Gate | Control electrode; requires negative bias relative to source to enable conduction |
| Pin 3 (Right) | Source | Reference terminal for gate drive and current return path; tied to system ground or positive rail |
Key Features
| Feature | Design Value |
|---|---|
| P-channel enhancement mode | Enables high-side switching without level-shifting circuitry when source is tied to positive supply |
| Guaranteed RDS(on) ≤10 Ω | Ensures <175 mW conduction loss at full rated current, supporting thermally constrained PCB layouts |
| TO-92-compatible leadform | Allows direct replacement of legacy small-signal MOSFETs in existing through-hole designs |
| Low gate threshold range (-0.8 to -2.0 V) | Permits direct interface with 3.3 V or 5 V logic outputs without external gate drivers |
Applications
| Battery-Powered Load Switch | Logic-Level Signal Inversion |
|---|---|
Use Scenario: Enabling/disabling power to sensor modules in handheld medical devices during sleep cycles. IC Role / Device Role / Timing Role: High-side P-channel switch controlled by microcontroller GPIO. Use Value: Low RDS(on) minimizes voltage droop and self-heating during 100–200 mA active periods. | Use Scenario: Converting active-high logic signals to active-low outputs for legacy interface compatibility. IC Role / Device Role / Timing Role: Single-transistor inverter stage with pull-up resistor. Use Value: Verified 10 ns rise/fall times support clean signal transitions up to 10 MHz clock domains. |
| Portable Instrumentation Power Gating | Low-Voltage Level Translation |
Use Scenario: Isolating analog front-end circuitry from digital subsystems in multimeter designs. IC Role / Device Role / Timing Role: Standby-mode isolation switch between 3.3 V analog rail and digital core. Use Value: -100 nA max IDSS at 125°C prevents leakage-induced offset drift in precision measurement paths. | Use Scenario: Interfacing 1.8 V FPGA I/O to 3.3 V peripheral logic in compact IoT edge nodes. IC Role / Device Role / Timing Role: Bidirectional level shifter using gate-driven source-follower configuration. Use Value: Gate threshold range allows robust turn-on with 1.8 V logic high while maintaining noise margin against VGS(th) variation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar P-channel low-power switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ZVP3306A | VDS = -60 V, RDS(on) = 12 Ω @ VGS = -10 V - higher voltage rating but higher on-resistance at logic-level drive | Preferred where >50 V transient immunity required; less suitable for 3.3 V gate drive | Select if system must withstand >50 V load dump events; verify gate drive capability matches VGS(th) distribution |
| DMG2305UVT | SO-8 package, RDS(on) = 45 mΩ @ VGS = -4.5 V - lower resistance but surface-mount only and higher gate charge | Optimized for automated assembly and higher-current loads (>500 mA); incompatible with through-hole layouts | Choose for volume SMT production requiring <50 mΩ on-resistance; not a drop-in replacement for TO-92 footprints |
Compared with ZVP4105ASTOA, ZVP3306A offers higher voltage margin but reduced logic-level drivability, while DMG2305UVT delivers significantly lower RDS(on) in SMT form but eliminates manual assembly compatibility and increases gate drive demand.
Availability
ZVP4105ASTOA is available at Aetrix Electronics and suitable for battery-powered load switching, logic-level inversion, portable instrumentation power gating, and low-voltage level translation requiring stable component supply across design-in, prototyping, and low-volume production phases.
Supply support for ZVP4105ASTOA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Zetex Semiconductors, now part of Diodes Incorporated, specialized in high-performance discrete semiconductors for precision analog and power-efficient digital systems.
ZVP4105ASTOA belongs to the ZVP series of P-channel enhancement-mode vertical DMOS FETs designed specifically for low-power, logic-compatible switching in space-constrained portable and battery-operated equipment.
FAQ
What is the maximum safe gate-source voltage for ZVP4105ASTOA?
The absolute maximum VGS is ±20 V. Exceeding this risks irreversible gate oxide damage. For reliable operation, gate drive should remain within -12 V to +5 V, with typical use at -5 V for full enhancement. Transient spikes above ±15 V require clamping diodes or RC snubbers in high-noise environments.
Can ZVP4105ASTOA be used as a high-side switch with 3.3 V logic control?
Yes - its gate threshold range of -0.8 V to -2.0 V ensures turn-on with 3.3 V logic high referenced to source. When source is at 3.3 V, applying 0 V to gate yields -3.3 V VGS, well within the conduction region. No level shifter is needed, but ensure gate drive sink capability meets 10 nA IGSS specification.
How does temperature affect RDS(on) in ZVP4105ASTOA?
RDS(on) increases with junction temperature, typically +0.5%/°C. At 125°C, it rises to approximately 13.5 Ω versus 10 Ω at 25°C. This must be factored into thermal design: at -175 mA, power dissipation climbs from 306 mW to ~340 mW, requiring adequate copper area or forced airflow in sealed enclosures.
Is ZVP4105ASTOA RoHS compliant and halogen-free?
Yes - as manufactured by Diodes Incorporated post-acquisition, ZVP4105ASTOA meets RoHS Directive 2011/65/EU and is certified halogen-free per IEC 61249-2-21. The TO-92 package uses matte tin-plated leads and epoxy molding compound compliant with JEDEC J-STD-020 moisture sensitivity level 1.
ZVP4105ASTOA Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Diodes Incorporated
- Series:
- -
- Package/Case:
- E-Line-3
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- P-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 50 V
- Current - Continuous Drain (Id) @ 25°C:
- 175mA (Ta)
- Drive Voltage (Max Rds On, Min Rds On):
- 5V
- Rds On (Max) @ Id, Vgs:
- 10Ohm @ 100mA, 5V
- Vgs(th) (Max) @ Id:
- 2V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- -
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 40 pF @ 25 V
- FET Feature:
- -
- Power Dissipation (Max):
- 625mW (Ta)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- E-Line (TO-92 compatible)
ZVP4105ASTOA FAQ
1.How can I place an order for ZVP4105ASTOA through Aetrix?
Please submit a Request for Quotation (RFQ) for ZVP4105ASTOA on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ZVP4105ASTOA reliable?
The price and inventory of ZVP4105ASTOA are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ZVP4105ASTOA is usually 5 days.
3.What payment methods are accepted for ZVP4105ASTOA?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ZVP4105ASTOA transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ZVP4105ASTOA?
ZVP4105ASTOA orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ZVP4105ASTOA order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ZVP4105ASTOA?
For technical support, including ZVP4105ASTOA datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ZVP4105ASTOA requirements.
6.How does Aetrix verify that ZVP4105ASTOA is sourced from the original manufacturer or authorized distributors?
All ZVP4105ASTOA products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ZVP4105ASTOA meets industry standards.
7.What is the process for return or replacement of ZVP4105ASTOA?
All ZVP4105ASTOA units undergo pre-shipment inspection (PSI). If there is an issue with ZVP4105ASTOA, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ZVP4105ASTOA part is unused and in its original packaging.
Return procedure for ZVP4105ASTOA:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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