STMicroelectronics MASTERGAN1L

Overview

MASTERGAN1L from STMicroelectronics is a 600 V system-in-package integrating a high-voltage half-bridge gate driver and two enhancement-mode GaN HEMTs in monolithic QFN 9 × 9 mm package. It delivers R_DS(on) = 150 mΩ (T_J = 25 °C), I_DS(MAX) = 9.7 A DC, zero reverse recovery charge (Q_RR = 0 nC), and <200 ns wake-up time - enabling high-frequency LLC resonant converters, active clamp flybacks, and high-efficiency 650 V DC-DC power supplies.

For engineers reviewing the MASTERGAN1L datasheet, MASTERGAN1L pinout, MASTERGAN1L application, or MASTERGAN1L equivalent, key selection considerations include bootstrap-enabled high-side drive, interlocking logic to prevent cross-conduction, integrated 6.5 V UVLO on VCC, -40 °C to 125 °C industrial operation, and internal 50 Ω/2 Ω gate resistors eliminating external tuning components.

Technical Context

The MASTERGAN1L implements a self-contained half-bridge topology with electrically isolated high-side and low-side GaN transistors sharing a common OUT node. Its level-shifting architecture uses an integrated bootstrap diode (R_DBoot = 175 Ω typ.) and internal VBO regulation to supply the floating high-side driver, eliminating external bootstrap diodes in most designs.

Logic control employs three dedicated pins (HIN, LIN, SD/OD) with internal pull-downs (150 kΩ typ.), hysteresis (0.96 V), and interlocking that forces both outputs low when HIN and LIN are simultaneously high. Overtemperature protection triggers shutdown at T_TSD = 175 °C with 20 °C hysteresis, and UVLO ensures safe operation with V_CCthON = 4.5 V and 0.3 V hysteresis.

Key Specifications

Pinout & Package

MASTERGAN1L is housed in a thermally enhanced QFN 9 × 9 × 1 mm package with three exposed pads (EP1, EP2, EP3) for thermal management: EP1 connects to GND, EP2 to SENSE (low-side source), and EP3 to VS (high-side drain). The 31-pin layout integrates dual GaN sources/sinks, bootstrap supply, and logic interfaces in a single compact footprint.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage GaN half-bridge applications.

Compared with GS66508B and TP65H035G4PS, MASTERGAN1L reduces bill-of-materials by 9 components, cuts layout area by 40%, and embeds safety-critical functions (interlock, UVLO, OT) in silicon - making it optimal for space-constrained, high-reliability resonant power supplies.

Availability

MASTERGAN1L is available at Aetrix Electronics and suitable for high-frequency resonant converters, active clamp flybacks, and high-voltage DC-DC power supplies requiring stable component supply, long-term lifecycle assurance, and production-ready qualification.

Supply support for MASTERGAN1L includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, power, microcontroller, and sensor solutions for industrial, automotive, and consumer markets.

MASTERGAN1L belongs to ST's MasterGaN family of GaN system-in-package devices, engineered specifically to accelerate adoption of gallium nitride in high-efficiency, high-frequency AC-DC and DC-DC conversion - targeting 100+ kHz to 2 MHz operation with minimal design overhead.

FAQ

What is the maximum recommended switching frequency for MASTERGAN1L?

MASTERGAN1L is characterized and optimized for operation up to 2 MHz, with verified performance in LLC resonant converters at 800 kHz and active clamp flybacks at 1 MHz. Key enablers include 100 V/ns slew rate, 45 ns propagation delays, and zero Q_RR. Thermal limits depend on PCB layout: with 6 thermal vias per exposed pad on a 4-layer board, continuous operation at 1 MHz is achievable at ≤60 W dissipation per GaN transistor.

How is the bootstrap capacitor value calculated for MASTERGAN1L?

The minimum bootstrap capacitance is determined by C_BOOT,min ≥ Q_BO / V_BOripple, where Q_BO = Q_G + I_qBO@HINon·δ_HS/f_sw + I_LK·(1−δ_LS)/f_sw, and V_BOripple = 250 mV. For f_sw = 500 kHz, δ_HS = 0.45, and typical Q_G = 2 nC, C_BOOT,min ≈ 22 nF. ST recommends 33 nF X7R ceramic placed within 2 mm of BOOT and OUTb pins to ensure stable V_BO under all load conditions.

Does MASTERGAN1L require external anti-parallel diodes?

No - MASTERGAN1L's GaN transistors support bidirectional conduction with V_SD ≈ I_S·R_DS(on) during on-state and sub-1 V drop during off-state reverse conduction, eliminating reverse recovery losses. However, ST recommends adding external Schottky diodes across each GaN in resonant topologies to reduce dead-time conduction loss and improve light-load efficiency, especially when ZVS margin is tight.

What thermal interface materials are recommended for MASTERGAN1L's exposed pads?

For EP1 (GND), EP2 (SENSE), and EP3 (VS), ST specifies minimum 100 mm² copper area per pad with ≥6 thermal vias (0.3 mm diameter, filled or plated) connecting to inner ground/power planes. No thermal interface material is required between die and package - the QFN's direct copper exposure provides sufficient thermal path. For ambient temperatures above 85 °C, forced airflow ≥1 m/s over the top surface reduces R_th(J-A) from 17.5 °C/W to ~12 °C/W.