STMicroelectronics MASTERGAN1LTR

Overview

MASTERGAN1LTR from STMicroelectronics is a 600 V system-in-package integrating a half-bridge gate driver and two enhancement-mode GaN HEMTs in monolithic QFN 9 × 9 mm package. It delivers R_DS(ON) = 150 mΩ (T_J = 25 °C), I_DS(MAX) = 9.7 A DC, zero reverse recovery charge, and ultra-fast wake-up time < 200 ns - enabling high-frequency resonant topologies such as LLC and active clamp flyback in compact power adapters and industrial DC-DC converters.

For engineers reviewing the MASTERGAN1LTR datasheet, MASTERGAN1LTR pinout, MASTERGAN1LTR application, or MASTERGAN1LTR equivalent, key selection considerations include its integrated bootstrap diode, interlocking logic to prevent cross-conduction, 3.3–15 V logic-compatible inputs with hysteresis, dedicated shutdown/overtemperature pin (SD/OD), and thermal resistance R_th(J-CB) = 1.9 °C/W per GaN transistor.

Technical Context

The MASTERGAN1LTR embeds two 650 V GaN transistors in half-bridge configuration: low-side drain connected to OUT pins, source to SENSE pins; high-side drain to VS pins, source to OUT pins. Its level-shifted driver uses internal bootstrap (VBO referenced to OUTb) and features fixed RG_ON/RG_OFF resistors (50 Ω / 2 Ω) for precise slew rate control (100 V/ns) and minimized crossover time (15 ns on/off).

Logic interface includes three inputs - HIN, LIN, and SD/OD - with internal pull-downs (90–220 kΩ), hysteresis (0.7–1.2 V), and interlocking that forces both GaNs OFF when HIN and LIN are simultaneously high. UVLO on VCC (4.2–4.75 V turn-on, 3.9–4.5 V turn-off) ensures safe operation under undervoltage conditions.

Key Specifications

Pinout & Package

MASTERGAN1LTR is housed in a thermally enhanced QFN 9 × 9 × 1 mm package with three exposed thermal pads (EP1, EP2, EP3) tied to GND, SENSE, and VS respectively. The 31-pin layout integrates dual GaN sources/sinks, isolated high-side supply routing, and logic-level inputs with built-in ESD protection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge GaN power stage applications.

Compared with GS66508T and LMG3425R030, MASTERGAN1LTR offers the highest level of integration (bootstrap diode, interlock, OT reporting, and matched timing), smallest footprint (9 × 9 mm), and lowest total system BOM count - making it optimal for cost-sensitive, high-volume adapter and charger designs below 150 W.

Availability

MASTERGAN1LTR is available at Aetrix Electronics and suitable for high-frequency resonant converters, active clamp flybacks, and industrial DC-DC power supplies requiring stable component supply, consistent parametric performance, and long-term lifecycle support.

Supply support for MASTERGAN1LTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, MCU, power, and sensor solutions for industrial, automotive, and consumer markets.

MASTERGAN1LTR belongs to ST's MASTERGAN family of GaN system-in-package devices, engineered specifically to replace discrete Si MOSFET + driver combinations in high-efficiency, high-power-density SMPS - targeting USB PD, server PSUs, and renewable energy interfaces.

FAQ

What is the recommended minimum deadtime for MASTERGAN1LTR in LLC operation?

The datasheet specifies a suggested minimum deadtime of 10 ns to prevent cross-conduction. However, due to its 15 ns crossover time (t_C(on/off)) and hardware interlocking, actual deadtime can be set as low as 25 ns in production designs - verified with oscilloscope measurement of GH/GL overlap under worst-case V_CC, temperature, and load conditions.

Is an external Zener diode required on the GH–OUTb path?

Yes - a 6.8 V Zener diode (e.g., BZX84-C6V8) is mandatory between GH and OUTb. During reverse conduction, V_SD on the low-side GaN adds to BOOT voltage, risking GH overvoltage beyond the 7 V absolute max rating. ST confirms this in DS14355 Section 5.2 and shows the Zener in Figures 19–21.

Can MASTERGAN1LTR operate with 3.3 V logic inputs?

No - although inputs accept 3.3–15 V, the logic threshold (V_IL = 1.1–1.45 V, V_IH = 2.0–2.5 V) and hysteresis (0.7–1.2 V) require ≥4.5 V for reliable high-level recognition. At 3.3 V, HIN/LIN may fall within the indeterminate region; ST recommends ≥4.75 V V_CC for guaranteed operation.

How is thermal performance affected by PCB layout?

Thermal resistance R_th(J-CB) = 1.9 °C/W assumes 2s2p FR4 board with six 0.3 mm vias per exposed pad (EP1/GND, EP2/SENSE, EP3/VS). Reducing via count to four increases R_th by 18%; omitting EP2 copper pour raises low-side junction temperature by 22 °C at 6 A continuous - per DS14355 Figure 13 derating curve.