STMicroelectronics MASTERGAN3TR

Overview

MASTERGAN3TR from STMicroelectronics is a 600 V system-in-package integrating an asymmetrical half-bridge gate driver and two enhancement-mode GaN transistors (HS: 450 mΩ, LS: 225 mΩ; IDS(MAX) = 4 A HS / 6.5 A LS) in a single QFN 9 × 9 × 1 mm package. It enables high-frequency, high-efficiency switching in compact AC-DC and DC-DC converters with integrated bootstrap diode, interlocking, UVLO on both sides, and thermal shutdown.

For engineers reviewing the MASTERGAN3TR datasheet, MASTERGAN3TR pinout, MASTERGAN3TR application, or MASTERGAN3TR equivalent, this device supports fast design of high-density 650 V GaN-based power stages requiring precise timing match, reverse-current capability, and simplified layout with bill-of-materials reduction.

Technical Context

The MASTERGAN3TR implements a fully integrated half-bridge topology with independent logic inputs (HIN/LIN/SD/OD), internal level-shifting, and matched propagation delays (46 ns each) between high-side and low-side paths. Its patented bootstrap structure uses an integrated high-voltage DMOS to supply the floating high-side driver without external diodes below 500 kHz.

UVLO protection operates independently on VCC (4.2–4.5 V turn-on) and VBO (3.6–4.0 V turn-on), while interlocking prevents cross-conduction by synchronizing input transitions. Thermal shutdown (175 °C trip, 20 °C hysteresis) forces SD/OD low and places the bridge in high-impedance state.

Key Specifications

Pinout & Package

MASTERGAN3TR is housed in a thermally enhanced QFN-31 (9 × 9 × 1 mm) package with three exposed pads (EP1, EP2, EP3) for GND, SENSE, and OUT connections. The package supports high-power dissipation via bottom-side thermal vias and provides isolation between high-voltage (VS), low-voltage (GND/PVCC/VCC), and gate-drive (GL/GH) domains.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage GaN half-bridge applications.

Compared with GS66508T and NV6128, MASTERGAN3TR uniquely combines asymmetric R_DS(on) optimization, integrated bootstrap, hardware interlock, and industrial-grade thermal protection-making it optimal for high-efficiency, high-reliability 65–100 W PFC and DC-DC designs where layout simplicity and robustness are prioritized over ultimate miniaturization or discrete tuning.

Availability

MASTERGAN3TR is available at Aetrix Electronics and suitable for high-voltage PFC stages, USB-C PD fast chargers, industrial DC-DC converters, and server intermediate bus converters requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for MASTERGAN3TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog devices for industrial, automotive, and consumer markets.

MASTERGAN3TR belongs to ST's MASTERGAN family of GaN-integrated power systems, engineered specifically to accelerate adoption of gallium nitride in high-frequency, high-efficiency AC-DC and isolated DC-DC conversion for data centers, EV infrastructure, and premium consumer power supplies.

FAQ

What is the recommended minimum dead-time for MASTERGAN3TR?

The datasheet specifies a suggested minimum dead-time of 5 ns to prevent cross-conduction. This value accounts for the matched 46 ns propagation delays and internal interlocking logic. For reliable operation under worst-case timing skew and temperature variation, designers should implement ≥15 ns dead-time in gate driver PWM generation or use the built-in interlock to enforce hardware-level blanking.

Can MASTERGAN3TR operate without an external bootstrap capacitor?

No - MASTERGAN3TR requires an external bootstrap capacitor between BOOT and OUTb pins. The integrated bootstrap diode charges this capacitor during low-side conduction but does not eliminate the need for the capacitor itself. A typical value is 100 nF X7R ceramic placed adjacent to the BOOT/OUTb pins to maintain stable high-side supply during HS switching.

How does the SD/OD pin behave during thermal shutdown?

During thermal shutdown, the SD/OD pin is actively pulled low as an open-drain output, signaling fault condition to the host controller. It remains low until junction temperature drops below (175 °C − 20 °C) = 155 °C AND the SD/OD pin voltage rises above 2.7 V (V_ih). This dual-condition release prevents premature re-enablement during thermal recovery transients.

Is MASTERGAN3TR pin-compatible with earlier MASTERGAN variants?

No - MASTERGAN3TR uses a unique 31-pin QFN layout with distinct pin assignments (e.g., dedicated OUTb, multiple SENSE/VS/OUT pads) and is not pin-compatible with MASTERGAN1 or MASTERGAN2. Migration requires PCB redesign and firmware validation due to differences in shutdown behavior, UVLO thresholds, and thermal response characteristics.