Monolithic Power Systems Inc. MP86920GLV-P

Overview

MP86920GLV-P from Monolithic Power Systems is a monolithic half-bridge Intelli-Phase™ solution integrating high-side and low-side power MOSFETs, gate drivers, current sense, and temperature sense in a single LGA-27 (4mm×5mm) package. It delivers 20A continuous output current, operates from 4.5V to 16V input, supports 100kHz–2MHz switching, and features tri-state PWM acceptance for diode emulation-optimized for server VRMs and multi-phase buck regulators.

For engineers reviewing the MP86920GLV-P datasheet, MP86920GLV-P pinout, MP86920GLV-P application, or MP86920GLV-P equivalent, key selection criteria include integrated HS/LS FET R_DS(on) matching, 3ns rising / 8ns falling dead time, bidirectional CS gain (10μA/A), TMON/FLT dual-mode junction sensing (8mV/°C) and fault reporting, and LGA thermal performance (θ_JB = 4.3°C/W).

Technical Context

The MP86920GLV-P implements a fully integrated half-bridge power stage with level-shifted gate drive architecture, enabling synchronous rectification without external bootstrap diodes. Its internal driver controls matched silicon-based HS/LS FETs with precise dead-time control (3ns rising, 8ns falling for positive current) and negative-current limiting (−15A, 40ns off-time).

It embeds analog front-end functions: a ratiometric current-sense output (10μA/A, ±2% gain accuracy, 0.8–2.0V common-mode range) and a dual-function TMON/FLT pin providing 8mV/°C temperature sensing (800mV offset at 25°C) or open-drain fault signaling at 3.3V during over-current, over-temperature (>160°C), or SW-to-PGND short events.

Key Specifications

Pinout & Package

LGA-27 (4mm × 5mm) package with exposed thermal pad on bottom; requires controlled-depth solder paste stencil (0.10mm max coplanarity) and JEDEC MO-303-compliant land pattern. Pin 1 identified by index marking; no lead finish specified beyond RoHS-compliant, halogen-free construction.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge power stage applications.

Compared with MP86950GLV-P and IR35221, the MP86920GLV-P uniquely combines 20A capability, analog CS + TMON/FLT dual telemetry, and bootstrap-integrated LGA-27 packaging-making it optimal for analog-controlled, space-constrained, thermally aware multi-phase server VRMs.

Availability

MP86920GLV-P is available at Aetrix Electronics and suitable for server voltage regulators, graphics card core regulators, and telecom baseband units requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant manufacturing.

Supply support for MP86920GLV-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with design centers in the US, China, and Taiwan, and global distribution through authorized partners.

The MP86920 belongs to MPS's Intelli-Phase™ family-engineered specifically for high-efficiency, high-density, multi-phase DC/DC conversion in datacenter and AI infrastructure where thermal telemetry, current sensing fidelity, and layout simplicity are critical.

FAQ

What is the maximum allowable VIN transient voltage for MP86920GLV-P?

The absolute maximum VIN transient rating is +25V for 25ns pulses, with DC limit at 18V. Exceeding +25V even briefly risks permanent damage to the integrated HS-FETs. System designers must ensure input filtering limits transients to ≤22V under worst-case surge conditions per IEC 61000-4-5.

Can MP86920GLV-P operate without an external bootstrap diode?

Yes-the MP86920GLV-P integrates an internal bootstrap switch, eliminating the need for an external diode. The BST pin connects directly to a 0.1–1µF ceramic capacitor referenced to the PHASE node, simplifying layout and improving reliability in high-reliability server applications.

How does the TMON/FLT pin differentiate between temperature reading and fault reporting?

When active and fault-free, TMON/FLT outputs a linear 8mV/°C voltage with 800mV offset (e.g., 0.8V at 25°C). During any fault-over-current, over-temperature (>160°C), or SW-to-PGND short-the pin is actively pulled to 3.3V regardless of temperature, providing unambiguous fault signaling to the host controller.

What is the minimum recommended input capacitance for MP86920GLV-P at 12V input?

MPS recommends ≥22µF total ceramic input capacitance (e.g., four 5.6µF 0805 X7R MLCCs) placed directly across VIN and PGND pins. This value ensures <50mV input ripple at 20A load with 800kHz switching and meets the 150nH inductor requirement specified in the typical application circuit.

Does MP86920GLV-P support forced continuous conduction mode (FCCM)?

No-the MP86920GLV-P only supports PWM and tri-state (diode emulation) modes. It lacks a dedicated FCCM control input or internal logic to override zero-current detection. For FCCM operation, an external controller must hold PWM high continuously, disabling ZCD-based LS-FET turn-off.

What is the thermal resistance from junction to case top (θJC_TOP) for MP86920GLV-P?

The θJC_TOP is 18.7°C/W, measured from junction to the top surface of the LGA-27 package. This value informs heatsink or thermal pad interface design when top-side cooling is implemented-though primary thermal path is through the exposed PGND pad to the PCB.

Is the CS pin output truly bidirectional, and how is negative current sensed?

Yes-the CS pin sinks or sources current proportional to inductor current direction: +10μA/A for positive current, −10μA/A for negative current. When inductor current goes negative, the CS output reverses polarity, enabling controllers to detect reverse conduction and trigger appropriate phase management or protection actions.