Monolithic Power Systems Inc. MP86935-AGLJT-P

Overview

MP86935-AGLJT-P from Monolithic Power Systems is a monolithic half-bridge Intelli-Phase™ power stage integrating high-side and low-side MOSFETs, gate drivers, Accu-Sense™ current sensing, and junction temperature monitoring. It delivers 60A continuous output current, operates from 3V–12V input, supports 100kHz–3MHz switching, and features tri-state PWM control for diode emulation and standby modes. It is designed for high-density server core voltage regulation.

For engineers reviewing the MP86935-AGLJT-P datasheet, MP86935-AGLJT-P pinout, MP86935-AGLJT-P application, or MP86935-AGLJT-P equivalent, key selection criteria include its integrated 60A current capability, TLGA-35 thermal performance (θJB = 2.2°C/W), tri-state PWM interface compatibility, bidirectional current-sense accuracy (±2% at 20–60A), and fault reporting via VTEMP/FLT pin.

Technical Context

The MP86935-AGLJT-P implements a synchronous buck half-bridge topology with integrated HS/LS FETs and driver logic optimized for multi-phase VR14/VR15-compliant CPU/GPU regulators. Its functional block includes zero-current detection (ZCD), cycle-by-cycle high-side current limiting (90A), and negative inductor current limiting (−30A) with 200ns off-time.

It uses a bootstrap gate drive architecture (BST pin with 0.1–1µF capacitor) and requires external 3.3V bias for VDRV and VDD (decoupled via 2.2Ω resistor and 1µF cap to AGND). Thermal sensing (10mV/°C gain, −100mV offset at 25°C) and fault latching (OTP at 160°C, SW-to-PGND short, overcurrent) are implemented on the VTEMP/FLT pin.

Key Specifications

Pinout & Package

MP86935-AGLJT-P is housed in a thermally enhanced TLGA-35 (3mm × 6mm) package with exposed PGND pads on the bottom for optimal heat dissipation and low-inductance power routing. The package complies with JEDEC MO-303 and supports reflow per MSL Level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-current Intelli-Phase™ power stage applications.

Compared with MP86933-AGLJT-P, the MP86935-AGLJT-P delivers 50% higher current capacity and superior thermal performance (2.2 vs. 2.5°C/W), while versus ISL99390HRZ-T it offers tighter integration via dual-role VTEMP/FLT and eliminates need for external thermal components-reducing total solution size by ~12%.

Availability

MP86935-AGLJT-P is available at Aetrix Electronics and suitable for server core voltage regulation, GPU power delivery, and AI accelerator modules requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for MP86935-AGLJT-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over two decades of innovation in DC/DC conversion, motor drivers, and power modules.

The MP86935-A belongs to MPS's Intelli-Phase™ family-engineered specifically for high-current, high-efficiency, multi-phase CPU/GPU VR applications where integration, thermal performance, and digital telemetry (current/temp/fault) are critical.

FAQ

What is the recommended input capacitance for MP86935-AGLJT-P?

Place multiple low-ESR MLCCs (e.g., 10× 10µF 0603 or 0402) directly adjacent to VIN and PGND pins-preferably on the same PCB layer-with ≥12 vias connecting VIN/PGND pads to inner-plane copper. Total input capacitance should be ≥100µF to suppress voltage spikes during 60A transients.

How does the tri-state PWM function enable diode emulation mode?

When PWM is driven to a middle voltage (1.1–1.95V at VDD=3.6V) or left floating, the internal current source pulls it to ~1.5V, triggering immediate HS-FET turn-off and LS-FET conduction until zero-current detection occurs. This eliminates reverse recovery losses in synchronous rectification, improving light-load efficiency by up to 8%.

Can MP86935-AGLJT-P operate without an external VDRV supply?

No. VDRV must be supplied externally with a stable 3.3V ±10% source capable of delivering ≥100mA peak current. It powers both gate drivers and internal logic; using VIN directly violates absolute max ratings and causes premature failure due to insufficient gate drive voltage under high dV/dt conditions.

What happens to the CS output during standby mode?

In standby mode (triggered by floating/middle SYNC for ≥2µs), the CS circuit is fully disabled-output goes high-impedance and provides no current-sense signal. The device requires 40µs to exit standby and resume accurate CS output after SYNC returns to valid logic level.

How is over-temperature protection implemented and reset?

OTP triggers at TJ > 160°C, latching off the HS-FET and pulling VTEMP/FLT to VDD. The fault persists until VIN or VDD is power-cycled-no software or pin-based reset exists. During latch, PWM is pulled to GND via 20kΩ, providing hardware-level fault signaling to the controller.

Is the TLGA-35 package compatible with standard reflow profiles?

Yes. MP86935-AGLJT-P is MSL Level 3 compliant and qualified for JEDEC J-STD-020D reflow. Peak temperature must not exceed 260°C, and time above 217°C shall be 60–150 seconds. Use recommended stencil design (0.12mm thickness, 1:1 aperture ratio) to ensure void-free solder joints on the exposed PGND thermal pad.