Monolithic Power Systems Inc. MP86950GLVT-P

Overview

MP86950GLVT-P from Monolithic Power Systems is a monolithic half-bridge Intelli-Phase™ solution integrating high-side and low-side power MOSFETs, gate drivers, Accu-Sense™ current sensing, temperature sensing, and fault reporting in a single TLGA-27 package. It delivers 50A continuous output current across 4.5V–16V input, supports 100kHz–2MHz switching, and enables diode emulation via tri-state PWM for server VR13/VR14 core regulators.

For engineers reviewing the MP86950GLVT-P datasheet, MP86950GLVT-P pinout, MP86950GLVT-P application, or MP86950GLVT-P equivalent, key selection criteria include its integrated 50A half-bridge topology, dual-function TMON/FLT pin (temperature sense + fault flag), ±30A/75A bidirectional current limit thresholds, dead time control (3–35ns), and compatibility with multi-phase buck controllers requiring accurate phase-current balancing and active voltage positioning.

Technical Context

The MP86950 operates as a self-contained half-bridge power stage with internal level-shifted gate drivers and zero-crossing detection (ZCD) logic to enable diode emulation mode. Its tri-state PWM interface accepts middle-voltage inputs (1.10–1.90V) to trigger LS-FET conduction during light-load conditions, reducing reverse recovery losses.

Current sensing uses a bidirectional 10μA/A CS output referenced to external V_CM, supporting cycle-by-cycle overcurrent protection and real-time inductor current monitoring. Fault management integrates three independent latching mechanisms-HS overcurrent (4-cycle), LS negative current (-30A), and junction overtemperature (>160°C)-all reported via the shared TMON/FLT pin.

Key Specifications

Pinout & Package

The MP86950GLVT-P is housed in a thermally enhanced TLGA-27 (4mm × 5mm) package with exposed PGND pads on the bottom for optimal heat dissipation and low-inductance power routing. The package features 27 terminals arranged in a 3×9 grid with pin 1 marked by an index area.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-current half-bridge power stage applications.

Compared with MP86951GLVT-P and ISL99390HRZ-T, the MP86950GLVT-P uniquely combines tri-state PWM compatibility, single-pin TMON/FLT telemetry, and 50A capability in a 4mm × 5mm footprint-making it optimal for space-constrained, thermally aware VR14-compliant server and GPU power stages where diode emulation and real-time current sensing are critical.

Availability

MP86950GLVT-P is available at Aetrix Electronics and suitable for server core voltage regulation, GPU power delivery, and high-density power modules requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for MP86950GLVT-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over two decades of innovation in DC/DC conversion, motor control, and power modules.

The MP86950 belongs to MPS's Intelli-Phase™ family of monolithic power stages, engineered specifically for high-efficiency, high-current VRM applications in cloud infrastructure, AI hardware, and graphics computing where integration, thermal performance, and signal fidelity are paramount.

FAQ

What is the recommended input capacitance for MP86950GLVT-P?

Place low-ESR MLCCs totaling ≥47μF (e.g., four 10μF 0402 or two 22μF 0603) directly between VIN and PGND pins, with minimal trace length and maximum via count under the pads. This ensures stable 90A pulsed current delivery and suppresses voltage ripple below 50mVpp at 1MHz switching.

How does the tri-state PWM mode function in MP86950GLVT-P?

The tri-state PWM mode activates when the PWM pin voltage remains within 1.10–1.90V for ≥40ns, causing the LS-FET to conduct during positive inductor current and turn off after zero-current detection. This eliminates body-diode conduction loss, improving light-load efficiency by up to 5% compared to standard PWM operation.

Can MP86950GLVT-P operate without an external bootstrap capacitor?

No. The BST pin requires a 0.1–1μF ceramic capacitor connected between BST and PHASE to generate the floating gate drive voltage for the high-side MOSFET. Omitting this capacitor prevents HS-FET turn-on and causes immediate fault latch via TMON/FLT pin pull-up to VDD.

What is the purpose of the CS pin's bidirectional current output?

The CS pin outputs a 10μA/A bidirectional current proportional to inductor current, enabling the host controller to perform real-time phase-current balancing, cycle-by-cycle overcurrent protection, and active voltage positioning. Its ±2% gain accuracy over 15–50A ensures precise droop control without external calibration.

How is over-temperature protection implemented in MP86950GLVT-P?

When junction temperature exceeds 160°C, the HS-FET latches off, the LS-FET turns on until zero-current detection, and the TMON/FLT pin is pulled high to VDD. Recovery requires cycling VIN, VDD, or EN-no automatic reset occurs to prevent thermal runaway during sustained overload conditions.

What PCB layout practices are critical for MP86950GLVT-P thermal performance?

Maximize PGND copper area and via count (≥12 vias) under pins 6,7,13,14,15,26; use inner-layer VIN plane aligned with top-side pads; place BST capacitor <2mm from pin 20 with >20-mil trace width; isolate CS trace from SW/PWM nodes using guard rings and AGND moats to preserve current-sense accuracy.