Monolithic Power Systems Inc. MP86952GMJ-P

Overview

MP86952GMJ-P from Monolithic Power Systems is a radiation-tolerant, monolithic half-bridge Intelli-Phase™ power stage integrating high- and low-side MOSFETs, gate drivers, Accu-Sense™ current sensing, and temperature-sense/fault reporting. It delivers up to 70A continuous output across 3V–16V input, operates from 100kHz to 3MHz, and targets high-density server core voltage regulation with LGA-41 (5mm×6mm) packaging.

For engineers reviewing the MP86952GMJ-P datasheet, MP86952GMJ-P pinout, MP86952GMJ-P application, or MP86952GMJ-P equivalent, this device supports tri-state PWM control, bidirectional inductor current monitoring (±70A), junction temperature reporting (8mV/°C), cycle-by-cycle overcurrent protection, and multi-phase thermal synchronization - critical for AI accelerator and CPU VRM designs requiring radiation tolerance and compact footprint.

Technical Context

The MP86952GMJ-P implements a synchronous buck half-bridge topology with integrated 16V-rated power MOSFETs and adaptive dead-time control (2ns rising / 6–28ns falling). Its Accu-Sense™ current-sense architecture delivers ±2% gain accuracy (5μA/A) and supports phase-current balancing and active droop via analog IOUT output (0.7–2.1V range).

Thermal management is enabled by dual-function TOUT/FLT pin (8mV/°C offset at 25°C, 160°C OTP latch), while fault detection covers HS overcurrent (8-cycle latch), LS negative current limit (−35A), SW-to-PGND short, and UVLO on VIN (2.5–3V) and VDD (2.75–2.95V).

Key Specifications

Pinout & Package

LGA-41 (5mm × 6mm) package with exposed thermal pad on underside; requires solder reflow per JEDEC J-STD-020, MSL Level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-current monolithic half-bridge applications.

Compared with MP86951GMJ-P and ISL99227BIRZ, the MP86952GMJ-P uniquely combines radiation tolerance, 70A analog power stage capability, and tri-state PWM compatibility - making it the sole option for space-qualified server VRMs and neutron-rich edge AI deployments.

Availability

MP86952GMJ-P is available at Aetrix Electronics and suitable for server core voltage regulation, AI accelerator GPU power delivery, and high-density telecom baseband units requiring stable component supply, long-term lifecycle assurance, and radiation-hardened performance.

Supply support for MP86952GMJ-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-efficiency, high-reliability power management ICs for computing, automotive, and industrial markets.

The MP86952 belongs to MPS's Intelli-Phase™ monolithic power stage product line, engineered specifically for high-current, high-frequency, radiation-tolerant VRM applications in mission-critical computing infrastructure.

FAQ

What is the maximum allowable input voltage for MP86952GMJ-P?

The absolute maximum VIN is 18V DC, but recommended operating range is strictly 3V to 16V. Exceeding 16V risks violating internal MOSFET oxide reliability margins and may trigger immediate UVLO shutdown at 18V transient peaks. Input capacitors must be rated for ≥25V to handle 10ns transients up to +32V.

How does the tri-state PWM function enable diode emulation mode?

When PWM voltage remains between 1.1V and 1.8V for ≥50ns, the MP86952GMJ-P disables HS-FET and activates LS-FET in diode emulation. The LS-FET stays on until zero-current detection occurs, then turns off - eliminating reverse recovery losses without requiring controller-level firmware updates or external circuitry.

Can IOUT be used for closed-loop current limiting without an external ADC?

No - IOUT is a current-source output (5μA/A) requiring an external resistor to convert to voltage (0.7–2.1V range). It cannot drive ADC inputs directly due to compliance voltage limits and lack of buffering. A precision op-amp buffer or dedicated current-to-voltage converter IC is required before ADC sampling.

What thermal interface material is recommended beneath the LGA-41 thermal pad?

MPS specifies no mandatory thermal interface; the exposed pad must be soldered directly to a solid PGND copper pour using standard reflow profile. Use solder paste with ≥90% metal content and avoid non-conductive pastes or gap fillers, which increase θJB by >1.5°C/W and risk delamination under thermal cycling.

Does MP86952GMJ-P support paralleling multiple units for >70A output?

Yes - the device supports seamless current sharing via synchronized PWM and shared TOUT/FLT for thermal alignment. However, phase interleaving must be implemented externally; the MP86952GMJ-P itself has no built-in clock synchronization or current-balancing logic - those functions reside in the master VR controller.

How is fault latching released after an over-temperature event?

A latch triggered by TJ >160°C is cleared only by toggling the EN pin low for ≥100ns or cycling VIN/VDD power. Simply cooling the die below 160°C does not auto-reset the latch - this prevents premature restart during thermal runaway conditions and ensures system-level intervention before resumption.

What is the minimum BST capacitor value and placement requirement?

The BST capacitor must be 0.1µF to 0.22µF ceramic, placed ≤2mm from BST and SW pins with trace width ≥20 mils and no vias in the loop. Smaller values risk insufficient gate drive during high-duty-cycle operation; longer traces induce ringing that degrades HS-FET turn-on timing and increases EMI.