Monolithic Power Systems Inc. MP86952GMJ-Z

Overview

MP86952GMJ-Z from Monolithic Power Systems is a radiation-tolerant, monolithic half-bridge Intelli-Phase™ power stage integrating high- and low-side MOSFETs, gate drivers, Accu-Sense™ current sensing, temperature sensing, and fault reporting. It delivers up to 70A continuous output across 3V–16V input, operates from 100kHz to 3MHz, and targets high-density server VRMs with LGA-41 (5mm×6mm) packaging.

For engineers reviewing the MP86952GMJ-Z datasheet, MP86952GMJ-Z pinout, MP86952GMJ-Z application, or MP86952GMJ-Z equivalent, key selection criteria include tri-state PWM compatibility, ±35A bidirectional current limit behavior, 8mV/°C junction temperature sensing accuracy, and integrated dead-time control for multi-phase buck regulators in radiation-aware environments.

Technical Context

The MP86952 implements a synchronous half-bridge topology with internal 3.3V logic-level gate drivers and optimized dead time (2ns rising / 6–28ns falling) to minimize shoot-through while supporting diode emulation mode via tri-state PWM. Its Accu-Sense™ current-sense output delivers 5μA/A gain with ±2% accuracy over 20–70A, enabling precise phase-current balancing and cycle-by-cycle OCP.

Thermal management integrates a dedicated TOUT/FLT pin providing 8mV/°C analog temperature output (800mV offset at 25°C) and open-drain fault signaling-latching on eight consecutive HS overcurrent events, >160°C junction temperature, or SW-to-PGND short-with distinct PWM pin resistance signatures (10kΩ, 20kΩ, or 1kΩ) for automated fault identification in multi-phase controllers.

Key Specifications

Pinout & Package

The MP86952GMJ-Z is housed in an LGA-41 (5mm × 6mm) package with exposed thermal pad on underside for board-level heat sinking. Pin layout supports high-current routing with 10 parallel PGND pins, 10 parallel SW pins, and 6 parallel VIN pins to minimize parasitic inductance and IR drop.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge power stage applications.

Compared with MP86951GMJ-Z, the MP86952GMJ-Z adds 20A headroom and radiation hardening at identical footprint; versus TPS53679RTAT, it trades PMBus configurability for analog simplicity, radiation resilience, and direct compatibility with analog PWM controllers.

Availability

MP86952GMJ-Z is available at Aetrix Electronics and suitable for server core voltage regulation, GPU power delivery, space-qualified point-of-load converters, and high-density telecom VRMs requiring stable component supply and long-term lifecycle assurance.

Supply support for MP86952GMJ-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over 20 years of leadership in DC-DC conversion, motor drivers, and power modules.

The MP86952 belongs to MPS's Intelli-Phase™ family-engineered specifically for high-current, high-frequency, radiation-aware power stages in mission-critical computing infrastructure where integration, reliability, and thermal efficiency are non-negotiable.

FAQ

What is the maximum allowable junction temperature before thermal shutdown?

The MP86952GMJ-Z triggers over-temperature protection (OTP) and latches off when junction temperature exceeds 160°C. The TOUT/FLT pin pulls high to VDD to indicate this fault, and the device remains latched until EN is toggled or VIN/VDD power is cycled. This threshold is fixed and not user-adjustable.

How does the tri-state PWM function enable diode emulation mode?

When the PWM input is held within the 1.1V–1.8V tri-state window for ≥50ns, the high-side FET turns off and the low-side FET enters diode emulation-conducting only during positive inductor current and turning off at zero-crossing. This eliminates reverse recovery losses and improves light-load efficiency without requiring a second control signal.

Can the IOUT pin be interfaced directly with a standard 12-bit ADC?

Yes-the IOUT pin outputs a 5μA/A current source with ±2% gain accuracy and requires an external resistor to develop 0.7–2.1V output. With a 200kΩ resistor to 1.2V reference, it produces 1.0–1.8V across 20–70A, fitting cleanly into a 12-bit ADC's 0–3.3V range with >10mV/A resolution and <0.5% quantization error.

What is the purpose of the PHASE pin (Pin 32)?

The PHASE pin connects to the bootstrap capacitor's high-side terminal and serves as the switching node reference for the floating high-side driver supply. It must be routed with low-inductance traces and paired with a 0.1–0.22μF ceramic capacitor between PHASE and BST to sustain gate drive voltage during high-side conduction-critical for reliable 70A operation at 3MHz.

Does the MP86952GMJ-Z require external bootstrap diodes or capacitors?

No external bootstrap diode is needed-the internal charge pump and level shifter eliminate it. However, a 0.1–0.22μF ceramic capacitor is mandatory between BST and PHASE pins to maintain high-side gate drive voltage. This capacitor must be placed within 2mm of the pins with ≥20-mil trace width and no vias in the BST path.

How is fault type distinguished on the TOUT/FLT and PWM pins?

TOUT/FLT asserts high for all faults, but PWM resistance changes uniquely per event: 10kΩ to AGND for overcurrent, 20kΩ to AGND for overtemperature, and 1kΩ to VDD for SW-to-PGND short. A simple resistor-divider and ADC reading on PWM-without additional pins-enables unambiguous fault classification in firmware.

Is the LGA-41 package lead-free and RoHS-compliant?

Yes-the MP86952GMJ-Z uses lead-free, halogen-free materials and fully complies with EU RoHS Directive 2011/65/EU and China RoHS II. MPS confirms green status on its Quality Assurance portal, and the device meets JEDEC J-STD-020 moisture sensitivity level (MSL) 3 per ordering information.