Monolithic Power Systems Inc. MP86957GMJ-Z

Overview

MP86957GMJ-Z from Monolithic Power Systems is a monolithic half-bridge Intelli-Phase™ solution integrating high-side and low-side power MOSFETs with gate drivers in a single 5mm×6mm LGA-41 package. It delivers 70A continuous output current, supports 3V–16V input range, operates up to 3MHz switching frequency, and features Accu-Sense™ current sensing and junction temperature reporting via TOUT/FLT - optimized for server core voltage regulation.

For engineers reviewing the MP86957GMJ-Z datasheet, MP86957GMJ-Z pinout, MP86957GMJ-Z application, or MP86957GMJ-Z equivalent, key selection criteria include tri-state PWM compatibility, ±40A valley current limiting, 2–28ns programmable dead time, and integrated fault flags (HS over-current, over-temperature, low-side catastrophic failure) for multiphase buck systems.

Technical Context

The MP86957GMJ-Z implements a fully integrated half-bridge topology with internal level-shifted gate drivers, zero-crossing detection (ZCD), and cycle-by-cycle current limiting on both high-side (95A limit) and low-side (−40A valley limit). Its tri-state PWM interface enables diode emulation mode without external control logic.

Thermal management is enabled by a dedicated TOUT/FLT pin providing 8mV/°C analog temperature output with 145°C over-temperature fault threshold and 12°C hysteresis, while IOUT delivers 5μA/A bi-directional current sense with ±2% gain accuracy across 20–70A load range.

Key Specifications

Pinout & Package

MP86957GMJ-Z uses an LGA-41 (5mm × 6mm) thermally enhanced land-grid array package with exposed PGND pads for low thermal resistance (θJB = 2.2°C/W) and high-current routing. The top-side pad layout separates power (VIN, SW, PGND), analog (AGND, VDD, VDRV), and signal (PWM, EN, IOUT, TOUT/FLT) domains to minimize coupling.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge power stage applications.

Compared with MP86956GMJ-Z and ISL99390HRZ-T, MP86957GMJ-Z uniquely combines 70A capacity, integrated temperature sensing, tri-state PWM compatibility, and multiphase fault aggregation - making it the only option for next-gen server VRMs requiring per-phase thermal awareness and diode emulation.

Availability

MP86957GMJ-Z is available at Aetrix Electronics and suitable for server core voltage regulation, GPU power delivery, AI accelerator modules, and telecom point-of-load converters requiring stable component supply, long lifecycle support, and traceable sourcing.

Supply support for MP86957GMJ-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP86957 belongs to MPS's Intelli-Phase™ family of integrated power stages, engineered specifically for high-efficiency, high-current multiphase buck converters in datacenter and AI infrastructure where thermal density and per-phase telemetry are critical.

FAQ

What is the recommended bootstrap capacitor value for MP86957GMJ-Z?

The BST pin requires a 0.1µF to 0.22µF ceramic capacitor connected between PHASE and BST pins. MPS specifies 0.22µF as optimal for 12V input operation to ensure sufficient gate drive voltage margin across temperature and load. Use X7R or better dielectric with low ESR, placed directly adjacent to the BST and PHASE pads with minimal trace length.

How does the tri-state PWM interface enable diode emulation mode?

When PWM is held within 1.10–1.80V (tri-state window) for ≥40ns, the MP86957 immediately turns off the HS-FET and enters diode emulation: the LS-FET conducts only during positive inductor current and turns off after zero-crossing detection. This eliminates body-diode conduction losses without requiring external control logic or ZCD circuitry.

Can multiple MP86957GMJ-Z devices share a single TOUT/FLT bus?

Yes - TOUT/FLT pins from multiple MP86957GMJ-Z units can be wire-OR'd together to report the highest junction temperature or first fault event to the controller. Each device sources current onto the shared line; no external pull-up is needed. This enables centralized thermal monitoring and fault prioritization in 4+ phase systems.

What is the purpose of the AGND and PGND separation in the MP86957GMJ-Z layout?

AGND isolates analog reference paths (VDD decoupling, current sense, temperature sense) from high-dI/dt power loops. Connecting AGND and PGND only at the VDD capacitor's ground pad prevents noise coupling into IOUT and TOUT/FLT signals - preserving ±2% current sense accuracy and <±2°C temperature reporting fidelity.

Does MP86957GMJ-Z support negative current limiting during light-load conditions?

Yes - the device actively limits negative inductor current to −40A using cycle-by-cycle valley detection. When triggered, it forces a 200ns HS-FET on-pulse to clamp reverse current, preventing excessive body-diode conduction and improving light-load efficiency without requiring external circuitry.

What is the maximum instantaneous current rating for MP86957GMJ-Z?

The absolute maximum instantaneous current is 95A, defined for ≤10ns pulses. This rating supports short-duration overload transients such as CPU turbo boost or GPU frame bursts, provided thermal design maintains junction temperature below 150°C and input capacitance limits peak dI/dt-induced voltage overshoot.

How is the IOUT pin calibrated for accurate current measurement?

IOUT provides 5μA/A with ±2% gain accuracy; calibration requires selecting RIOUT and VCM to keep VIOUT within 0.7–2.1V. For example, with 50A max current and 1.2V VCM, use RIOUT = 10kΩ to yield 1.7V output. Offset error is <±2μA at 25°C and <±1μA when EN = low, ensuring reliable disable-state detection.