Monolithic Power Systems Inc. MP86972GLJTH-P

Overview

MP86972GLJTH-P from Monolithic Power Systems is a monolithic half-bridge Intelli-Phase™ power stage integrating high-side and low-side MOSFETs, gate drivers, current sense (8 µA/A gain), temperature sense (10 mV/°C), and fault reporting in a single TLGA-35 (3mm × 6mm) package. It delivers 60 A continuous output current, operates from 3 V to 12 V input, supports 100 kHz–3 MHz switching, and targets server core voltage regulation with tri-state PWM compatibility.

For engineers reviewing the MP86972GLJTH-P datasheet, MP86972GLJTH-P pinout, MP86972GLJTH-P application, or MP86972GLJTH-P equivalent, key selection criteria include its integrated Accu-Sense™ current monitoring, dual-mode (CCM/diode emulation) operation via SYNC pin, ±30 A/90 A current-limit thresholds, thermal fault reporting at 160°C, and PCB layout-critical PGND/VIN via density requirements.

Technical Context

The MP86972 implements a synchronous buck half-bridge topology with integrated HS/LS FETs and driver logic optimized for multi-phase VR applications. Its tri-state PWM interface enables seamless transition to high-impedance SW state, while ZCD-based diode emulation reduces light-load losses. The device uses internal level-shifting and bootstrap circuitry (BST pin with 0.1–1 µF capacitor) to drive the HS-FET gate above VIN.

Thermal management is enabled by junction temperature sensing via VTEMP/FLT (10 mV/°C, −100 mV offset at 25°C), which doubles as a fault flag pulled to VDD on over-current, over-temperature (>160°C), or SW-to-PGND short events. Fault latching requires VIN/VDD power cycle for reset, and multi-phase systems share VTEMP/FLT pins for centralized thermal monitoring.

Key Specifications

Pinout & Package

MP86972GLJTH-P is housed in a thermally enhanced TLGA-35 (3 mm × 6 mm) package with exposed PGND pads on the bottom for low θJB (2.2°C/W) and efficient heat transfer to the PCB. The package features 35 terminals arranged in two rows, with dedicated high-current paths for VIN, PGND, and SW nodes.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar monolithic half-bridge power stage applications.

Compared with MP86932GLJTH-P, the MP86972GLJTH-P provides 50% higher current headroom and superior thermal performance (2.2 vs. 2.5°C/W θJB), while versus ISL99390HRZ-T it adds integrated thermal sensing and tri-state PWM-reducing system-level component count and enabling advanced efficiency modes.

Availability

MP86972GLJTH-P is available at Aetrix Electronics and suitable for server core voltage regulation, GPU power delivery, and AI accelerator module applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for high-reliability deployments.

Supply support for MP86972GLJTH-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over 20 years of expertise in DC/DC conversion, motor drivers, and power modules.

The MP86972 belongs to MPS's Intelli-Phase™ family of monolithic power stages, engineered specifically for high-current, high-efficiency server and AI infrastructure VRMs where integration, thermal performance, and digital control interface compatibility are critical.

FAQ

What is the recommended input capacitor configuration for MP86972GLJTH-P?

Place multiple 0603/0402 MLCCs as close as possible to the VIN and PGND pins, with ≥6 VIN vias and ≥9 PGND vias directly beneath the TLGA-35 package. Use a second-layer VIN copper plane in a positive/negative/positive stackup to minimize impedance. Total input capacitance should be ≥100 µF with low-ESR ceramics to handle 60 A switching transients.

How does the tri-state PWM function enable diode emulation mode?

When PWM is floated or driven to a mid-voltage (1.1–1.95 V at VDD = 3.3 V), the MP86972 immediately turns off the HS-FET and activates the LS-FET in diode emulation mode-turning it off only when inductor current reaches zero (ZCD). This eliminates reverse recovery losses and improves light-load efficiency without requiring controller-level ZCD circuitry.

Can MP86972GLJTH-P be used in multi-phase configurations with independent current sensing?

Yes - each MP86972GLJTH-P provides a dedicated CS pin with 8 µA/A gain and ±2% accuracy, enabling per-phase current measurement. For multi-phase thermal monitoring, connect all VTEMP/FLT pins together to a single ADC input; the highest junction temperature dominates the shared voltage, allowing centralized thermal throttling.

What is the minimum BST capacitor value and placement requirement?

A 0.1 µF ceramic capacitor is the minimum BST value; 0.22–1 µF is recommended for robustness. It must be placed directly between BST and SW pins with no vias in the loop, using ≥20-mil-wide traces. Improper placement causes HS-FET gate underdrive, leading to excessive conduction loss and thermal stress at high current.

How is over-temperature protection triggered and reset?

Over-temperature protection activates when junction temperature exceeds 160°C, pulling VTEMP/FLT to VDD and latching off the HS-FET. The fault persists until VIN or VDD is power-cycled - entering standby mode does not clear the latch. Reset requires full power-down to ensure thermal recovery before re-enabling switching.

Does MP86972GLJTH-P support both continuous conduction mode (CCM) and discontinuous conduction mode (DCM)?

It supports CCM (via SYNC high), diode emulation mode (SYNC low or PWM tri-state), and standby mode (SYNC tri-state for ≥2 µs), but does not implement true DCM with variable frequency or pulse-frequency modulation. Diode emulation provides DCM-like light-load efficiency while maintaining fixed-frequency operation for EMI control.

What is the significance of connecting AGND and PGND only at the VDD decoupling capacitor?

This single-point connection prevents high di/dt PGND noise from coupling into the analog current/temperature sense circuitry. Routing AGND separately to the VDD capacitor's ground pad isolates sensitive analog references from power-switching return paths, ensuring ±2% CS accuracy and stable VTEMP/FLT voltage readings under full 60 A load.