Monolithic Power Systems Inc. MP86972GLJTH-Z

Overview

MP86972GLJTH-Z from Monolithic Power Systems is a monolithic half-bridge Intelli-Phase™ power stage integrating high-side and low-side MOSFETs, gate drivers, Accu-Sense™ current sensing, and junction temperature monitoring in a single TLGA-35 (3mm × 6mm) package. It delivers 60A continuous output current, supports 100kHz–3MHz switching, and operates from 3V–12V input, targeting high-density server core voltage regulation.

For engineers reviewing the MP86972GLJTH-Z datasheet, MP86972GLJTH-Z pinout, MP86972GLJTH-Z application, or MP86972GLJTH-Z equivalent, key selection criteria include tri-state PWM compatibility, ±30A bidirectional current limit accuracy, 10mV/°C temperature-sense linearity, dead-time control (2–35ns), and fault reporting via VTEMP/FLT pin behavior under OTP, overcurrent, or SW-to-PGND short conditions.

Technical Context

The MP86972 implements a synchronous buck half-bridge topology with integrated HS/LS FETs and driver logic optimized for multi-phase VR applications. Its tri-state PWM interface enables seamless integration with digital controllers supporting diode emulation and high-impedance phase shedding.

It features cycle-by-cycle current limiting (90A HS, –30A LS), zero-current detection (ZCD) for diode emulation, and dual-function VTEMP/FLT pin providing linear junction temperature sensing (10mV/°C, –100mV offset at 25°C) plus open-drain fault flagging (pulled to VDD on fault). Thermal shutdown triggers at 160°C.

Key Specifications

Pinout & Package

MP86972GLJTH-Z uses a thermally enhanced TLGA-35 (3mm × 6mm) package with exposed PGND pads on bottom and top-side signal terminals. The package supports high-current routing via multiple VIN, PGND, and SW pins distributed across three sides for low-inductance layout.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-current half-bridge power stage applications.

Compared with MP86952GLJTH-Z, the MP86972GLJTH-Z provides 50% higher current capacity and superior thermal performance (θJB = 2.2°C/W vs. ~3.0°C/W), while versus ISL99390HRZ-T it integrates junction temperature sensing and fault reporting into one pin, reducing system-level sensing complexity and PCB area.

Availability

MP86972GLJTH-Z is available at Aetrix Electronics and suitable for server core voltages, GPU power delivery, and AI accelerator module supply requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for high-reliability deployments.

Supply support for MP86972GLJTH-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with expertise in DC/DC converters, motor drivers, and integrated power stages for computing and industrial markets.

The MP86972 belongs to MPS's Intelli-Phase™ product line-designed specifically for high-efficiency, high-current, multi-phase buck regulators in datacenter and AI hardware where power density, thermal intelligence, and system-level telemetry are critical.

FAQ

What is the function of the VTEMP/FLT pin?

The VTEMP/FLT pin serves two distinct roles: in active mode, it outputs an analog voltage proportional to junction temperature (10mV/°C with –100mV offset at 25°C); during any fault condition (over-temperature, overcurrent, or SW-to-PGND short), it becomes an open-drain fault flag pulled up to VDD (≥3.0V). This dual functionality eliminates the need for separate thermal and fault monitoring circuits.

How does tri-state PWM operation enable diode emulation?

When the PWM pin is driven to a middle-voltage (1.1–1.95V at VDD = 3.6V) or left floating, the internal circuitry disables the high-side FET and activates the low-side FET in diode-emulation mode. The LS-FET remains on until zero-current detection (ZCD) confirms inductor current has reached zero, minimizing reverse conduction losses during light-load conditions.

What is the recommended bootstrap capacitor value and placement?

A 0.1µF to 1µF ceramic capacitor must be placed directly between the BST and SW pins, with minimal trace length and no vias in the path. This capacitor supplies the gate drive voltage for the high-side FET and must be located within 2mm of both pins using ≥20-mil wide traces to ensure reliable switching at up to 3MHz.

Can MP86972GLJTH-Z operate without an external 3.3V supply?

No. The device requires an external 3.3V supply connected to both VDRV and VDD pins. VDRV powers the gate drivers, while VDD supplies internal logic; they are connected via a 2.2Ω resistor. Operating outside the 3.0V–3.6V range violates absolute maximum ratings and risks malfunction or damage.

What happens during standby mode and how is it triggered?

Standby mode is entered when the SYNC pin is floated or driven to a middle-voltage (1.1–1.95V) for ≥2µs. In this state, the device shuts down all switching activity, disables CS and VTEMP/FLT outputs, and reduces quiescent current to 90–180µA. Exiting standby requires reasserting a valid logic level on SYNC; the fault latch is not cleared by standby entry.

How is current-sense accuracy maintained across temperature and load?

Current-sense accuracy is specified as ±2% over 20A–60A at TJ = –40°C to +125°C, verified by characterization. The 8μA/A gain and low offset (±1–2μA) are achieved through matched on-die current mirrors and trimming. Maintaining CS pin voltage between 0.7V–2.1V using an external RCS resistor ensures full-range linearity and avoids saturation.

What PCB layout practices are critical for thermal performance?

Key practices include placing ≥8 VIN and ≥8 PGND vias under the TLGA-35 package, using a solid inner-layer VIN plane adjacent to the component layer, connecting AGND and PGND only at the VDD decoupling capacitor, and routing BST/VDRV capacitors with ≥20-mil traces directly adjacent to their pins. These reduce θJB to 2.2°C/W and prevent thermal runaway at 60A.