Monolithic Power Systems Inc. MP86992GMJ-Z

Overview

MP86992GMJ-Z from Monolithic Power Systems is a monolithic half-bridge Intelli-Phase™ power stage integrating high- and low-side MOSFETs, gate drivers, current sensing (5 µA/A gain), temperature sensing (8 mV/°C), and fault reporting in a single LGA-41 (5mm×6mm) package. It delivers 50 A continuous output current with 3–16 V input range, supports 100 kHz–3 MHz switching, and targets multi-phase buck regulators for server core voltage rails.

For engineers reviewing the MP86992GMJ-Z datasheet, MP86992GMJ-Z pinout, MP86992GMJ-Z application, or MP86992GMJ-Z equivalent, key selection criteria include tri-state PWM compatibility, Accu-Sense™ bidirectional current monitoring, integrated over-temperature (160°C) and cycle-by-cycle high-side current limit (75 A), and thermal performance enabled by θJB = 2.2°C/W in LGA-41 packaging.

Technical Context

The MP86992GMJ-Z implements a fully integrated half-bridge topology with level-shifted high-side driver, zero-current detection (ZCD) circuitry, and diode emulation mode triggered by tri-state PWM inputs. Its internal dead time control (2 ns rising / 6 ns falling for positive current) minimizes shoot-through while enabling high-frequency operation up to 3 MHz.

It features dual-sense architecture: IOUT provides proportional bidirectional current feedback (±50 A → ±250 µA), while TOUT/FLT serves as a shared junction temperature sensor (8 mV/°C, 800 mV offset at 25°C) and open-drain fault flag pulled to VDD during HS over-current, over-temperature (>160°C), or SW-PGND short events.

Key Specifications

Pinout & Package

LGA-41 (5 mm × 6 mm) package with exposed thermal pad on bottom side; requires solder paste stencil design per JEDEC MO-303 standard and strict coplanarity ≤ 0.10 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge power stage applications.

Compared with IR35221 and CSD97395Q4M, the MP86992GMJ-Z uniquely integrates bidirectional current sense, junction temperature sensing, and three-fault reporting into a single pin-reducing system-level component count, improving thermal visibility, and simplifying fault diagnostics in space-constrained, high-reliability server and AI hardware.

Availability

MP86992GMJ-Z is available at Aetrix Electronics and suitable for server core voltage regulation, GPU power delivery, AI accelerator supply, and high-density power modules requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for MP86992GMJ-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP86992 belongs to MPS's Intelli-Phase™ family-engineered specifically for high-current, high-efficiency, multi-phase DC/DC conversion in datacenter and AI infrastructure, where integration, thermal performance, and sensing fidelity are critical.

FAQ

What is the recommended layout for minimizing VIN-to-PGND loop inductance?

Place eight or more 0805 MLCCs directly adjacent to the VIN and PGND pads on both top and bottom layers; use ≥12 vias per VIN/PGND pad group connecting to inner-layer copper planes; route VIN and PGND traces with ≥20-mil width and avoid splits or necks in the power polygon. The goal is sub-200 pH loop inductance to suppress voltage spikes during 110 A peak current transitions.

How does the tri-state PWM interface improve light-load efficiency?

When PWM floats or is driven to 1.1–1.8 V, the MP86992 enters diode emulation mode: the low-side FET turns on during positive inductor current and turns off precisely at zero-crossing (ZCD), eliminating reverse recovery losses and body-diode conduction. This reduces light-load power loss by up to 15% compared to forced CCM operation.

Can IOUT be used for real-time over-current protection without a controller?

No-IOUT is a current-source output (5 µA/A) requiring an external op-amp or comparator with reference to convert to voltage and trigger shutdown. The MP86992's internal high-side current limit (75 A, 8-cycle latch) provides autonomous protection; IOUT serves primarily for controller-based monitoring and advanced functions like phase balancing and AVP.

What happens to TOUT/FLT during simultaneous over-temperature and over-current faults?

TOUT/FLT pulls high to VDD within 200 ns of the first fault occurrence-regardless of type-and remains asserted until EN is toggled or VIN/VDD is cycled. The pin does not distinguish concurrent faults; it signals "fault active" unambiguously. Fault type is decoded separately via PWM pin resistance (10kΩ/20kΩ/1kΩ) after TOUT/FLT assertion.

Is the BST capacitor value fixed, or can it be optimized?

The BST capacitor (0.1–0.22 µF ceramic) is not fixed-it must be selected based on switching frequency and duty cycle to maintain sufficient gate drive voltage during high-side conduction. At 3 MHz and 90% duty, 0.22 µF is recommended; at 500 kHz and 50% duty, 0.1 µF suffices. Use X7R/X5R dielectrics rated ≥16 V with low ESR.

Does the MP86992GMJ-Z support paralleling multiple units for >50 A per phase?

No-it is designed as a single 50 A phase-leg. Paralleling requires external current-sharing circuitry and introduces timing skew risks. For higher current, use multi-phase interleaving (e.g., four MP86992GMJ-Z units in 4-phase configuration), which provides natural current balancing via interleaved PWM and shared TOUT/FLT thermal telemetry.

How is AGND different from PGND, and why must they connect only at the VDD capacitor?

AGND carries low-noise analog reference currents (for IOUT, TOUT/FLT, UVLO); PGND handles high di/dt switching return paths. Connecting them only at the VDD decoupling capacitor's ground pad prevents noise coupling from PGND into analog circuits-ensuring ±2% current sense accuracy and stable 800 mV temperature offset calibration.