STMicroelectronics STDRIVEG600TR

Overview

STDRIVEG600TR from STMicroelectronics is a high-voltage half-bridge gate driver IC optimized for enhancement-mode GaN FETs and N-channel MOSFETs, featuring ±200 V/ns dV/dt immunity, 5.5/6 A source/sink drive capability at 15 V supply, 45 ns propagation delay with ≤10 ns matching, separated turn-on/turn-off pins, and integrated UVLO on both high- and low-side sections. It enables high-efficiency, high-frequency PFC and DC-DC converters up to 500 V bus voltage.

For engineers reviewing the STDRIVEG600TR datasheet, STDRIVEG600TR pinout, STDRIVEG600TR application, or STDRIVEG600TR equivalent, key selection considerations include bootstrap ruggedness under −210 V OUT spikes, TTL/CMOS-compatible 3.3 V logic inputs with hysteresis, interlocking to prevent cross-conduction, thermal shutdown signaling via open-drain SD/OD, and Kelvin-source–ready PGND/PVCC separation for GaN current-sense integrity.

Technical Context

The STDRIVEG600TR integrates dual independent output stages-high-side floating driver (600 V max) and low-side grounded driver-with dedicated level-shifted control paths, internal interlocking logic, and separate UVLO monitoring for VCC (logic rail) and VBO (BOOT–OUT floating rail). Its architecture supports hard-switching topologies with GaN devices by tolerating deep dynamic OUT below-ground excursions down to −210 V.

It employs a bootstrap-supplied high-side stage with integrated diode (R_D,boot = 140 Ω typ), Kelvin-source–capable PGND/PVCC rails for shunt-based current sensing, and an open-drain SD/OD pin that functions as both shutdown input and overtemperature fault indicator. Propagation delay matching (≤10 ns) and <7 ns rise/fall times ensure precise timing control in MHz-range switching applications.

Key Specifications

Pinout & Package

STDRIVEG600TR is housed in a 16-pin SOIC package (SO-16) with exposed pad for thermal performance. Pin 1 is marked with a dot; NC pins (6, 8, 12) must remain unconnected. Dedicated PGND and PVCC pins support Kelvin-source layout for accurate current sensing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage half-bridge gate driver applications.

Compared with UCC27712DR and IRS2007MTRPBF, STDRIVEG600TR uniquely combines GaN-grade dV/dt immunity, integrated interlocking, open-drain thermal fault signaling, and Kelvin-source–ready PGND-enabling compact, high-reliability designs in >1 MHz PFC, solar, and motor drive systems where timing precision and fault resilience are critical.

Availability

STDRIVEG600TR is available at Aetrix Electronics and suitable for high-voltage PFC converters, solar DC-AC inverters, and industrial motor drives requiring stable component supply, long-term lifecycle assurance, and traceable GaN-optimized gate driver sourcing.

Supply support for STDRIVEG600TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, mixed-signal, power, and microcontroller solutions for industrial, automotive, and consumer markets.

The STDRIVEG600TR belongs to ST's STDRIVE family of high-voltage gate drivers, engineered specifically for next-generation GaN and Si power stages in high-frequency, high-efficiency power conversion systems.

FAQ

What is the minimum BOOT voltage required for reliable high-side operation?

The STDRIVEG600TR requires BOOT–OUT (VBO) ≥ 5 V to propagate high-side commands reliably. Below this threshold, high-side turn-on may be delayed or missed-especially during hard-switching with GaN devices under high load current. The VBO UVLO turns off HON/HOFF at 3.7 V and re-enables at 4.0 V, providing 0.3 V hysteresis to prevent chatter.

How does the interlocking function prevent cross-conduction?

The interlocking logic monitors LIN and HIN simultaneously: if both inputs are high, it forces both LON/LOFF and HON/HOFF low regardless of input state, eliminating shoot-through risk. This hardware-level protection operates independently of timing margins or external dead-time generators, making it ideal for high-frequency GaN designs where nanosecond-level precision is critical.

Can STDRIVEG600TR drive silicon MOSFETs as well as GaN FETs?

Yes-STDRIVEG600TR is fully compatible with both enhancement-mode GaN HEMTs and standard N-channel Si MOSFETs. Its 6 A sink/source capability, 45 ns propagation, and ±200 V/ns dV/dt immunity benefit high-speed Si designs too, while its Kelvin-source PGND and bootstrap diode simplify layout for either technology. No configuration changes are needed.

What is the role of the SD/OD pin during thermal shutdown?

During thermal shutdown, the SD/OD pin is actively pulled low by an internal open-drain transistor, signaling overtemperature condition to the host controller. It remains low until junction temperature drops below (TTSD − THYS) = 155 °C and SD/OD voltage rises above 2.17 V. This dual-role pin eliminates need for external fault monitoring circuitry.