NXP Semiconductors UBA2033TS/N2,118

Overview

UBA2033TS/N2,118 from NXP Semiconductors is a high-voltage monolithic full-bridge gate driver IC fabricated in EZ-HV SOI process, designed to drive four external MOSFETs in resonant HID lamp ballasts. It integrates bootstrap diodes, high-voltage level shifters, an adjustable internal oscillator (up to 100 kHz), 550 V HV supply rating, and bridge disable functionality. It operates in high-frequency commutation for LC-resonant ignition of automotive and commercial HID lighting systems.

For engineers reviewing the UBA2033TS/N2,118 datasheet, UBA2033TS/N2,118 pinout, UBA2033TS/N2,118 application, or UBA2033TS/N2,118 equivalent, key selection considerations include its 550 V HV tolerance, integrated level-shifting for high-side drive, non-overlap time ≤250 ns, internal oscillator frequency adjustability via RC network, and SSOP28 package compatibility with HID lamp control topologies requiring precise dead-time control and robust start-up sequencing.

Technical Context

The UBA2033TS/N2,118 implements dual high-voltage level shifters enabling independent gate drive for two high-side (GHL/GHR) and two low-side (GLL/GLR) MOSFETs, with floating supply pins (FSL/FSR) referenced to respective high-side sources (SHL/SHR). Its oscillator supports three modes - internal RC-based, external clock with divider enabled (f_bridge = f_EXTDR/2), or external clock without divider (f_bridge = f_EXTDR) - all synchronized to falling edges on RC or EXTDR.

Start-up behavior is defined by UVLO thresholds (V_HV(rel) = 12.5 V typ., V_HV(UVLO) = 10 V typ.), during which lower-side MOSFETs conduct to charge bootstrap capacitors while higher-side outputs remain off. Bridge disable (BD ≥ 1.29 V) forces all gate outputs LOW regardless of oscillator or control state, providing hardware-level fault shutdown.

Key Specifications

Pinout & Package

UBA2033TS/N2,118 is housed in a plastic shrink small outline package (SSOP28) with 28 leads, 5.3 mm body width, and 0.65 mm lead pitch (SOT341-1). The package supports reflow soldering and is not recommended for wave soldering due to fine pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar full-bridge gate driver applications.

Compared with IRS2453D(S)PBF and MP6908AGS-Z, the UBA2033TS/N2,118 uniquely integrates dual high-voltage level shifters, full-bridge gate outputs, and resonant-mode oscillator in a single SSOP28 package - eliminating need for external level shifters, gate transformers, or discrete timing components in HID lamp ballast designs.

Availability

UBA2033TS/N2,118 is available at Aetrix Electronics and suitable for automotive lighting systems, commercial streetlight ballasts, industrial UV curing equipment, and HID lamp test instrumentation requiring stable component supply and long-term lifecycle support.

Supply support for UBA2033TS/N2,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in high-performance analog, mixed-signal, and power management ICs for automotive, industrial, and lighting applications.

The UBA2033TS/N2,118 belongs to NXP's UBA (Universal Ballast Architecture) product line, engineered specifically for high-efficiency, high-reliability electronic ballasts driving high-intensity discharge lamps in demanding environments.

FAQ

What is the maximum operating frequency of the UBA2033TS/N2,118 in internal oscillator mode?

The UBA2033TS/N2,118 supports a maximum bridge oscillation frequency of 100 kHz when using its internal RC oscillator. This limit arises from internal timing circuit design and ensures stable non-overlap timing and gate drive integrity. External oscillator mode extends this to 250 kHz, but requires disabling the internal divider (DD = HIGH) and connecting a clean external clock signal to EXTDR.

How does the UBA2033TS/N2,118 handle start-up sequencing for HID lamp ignition?

The UBA2033TS/N2,118 enters a defined start-up state when HV or VDD rises above UVLO threshold (≈10 V). During this phase, lower-side MOSFETs (GLL/GLR) conduct to charge bootstrap capacitors while high-side outputs remain inactive. Only after VDD exceeds release level (≈12.5 V) does oscillation begin - ensuring sufficient gate drive voltage before full bridge commutation starts. Pin SU allows adding RC delay for additional margin.

Can the UBA2033TS/N2,118 drive MOSFETs directly without external gate resistors?

No. The UBA2033TS/N2,118 datasheet explicitly recommends series gate resistors ≥100 Ω on all four gate drive outputs (GHL, GHR, GLL, GLR) to suppress EMC-induced transients during HID lamp ignition. Omitting these resistors risks voltage overstress on driver outputs due to gate-source ringing, especially during high-dV/dt events like spark generation in the ignitor circuit.

What is the purpose of the DD pin on the UBA2033TS/N2,118, and how does it affect bridge operation?

The DD (divider disable) pin controls whether the internal 2× frequency divider is active. When DD = LOW (connected to SGND), the divider is enabled, halving the oscillator frequency to produce exact 50% duty cycle at the bridge outputs - essential for symmetrical resonant current in HID applications. When DD = HIGH, the divider is bypassed, making bridge frequency equal to oscillator frequency and allowing asymmetric timing for specialized ignition sequences.

Does the UBA2033TS/N2,118 require an external low-voltage supply, or can it operate solely from the high-voltage rail?

The UBA2033TS/N2,118 can operate solely from the high-voltage rail applied to pin HV (up to 550 V), generating its own internal low-voltage supply (VDD ≈ 11.5 V) for logic and gate drivers. An external low-voltage supply to VDD is optional and only needed if HV is unavailable or insufficient - in that case, HV must be tied to VDD or SGND per datasheet guidance to avoid damage.