Nexperia USA Inc. NHUMB10F

Overview

NHUMB10 from Nexperia is a PNP/PNP resistor-equipped double transistor (RET) in SOT363 (SC-88) package, designed for digital switching and IC input control. It features 80 V collector-emitter breakdown voltage, −100 mA output current per transistor, built-in bias resistors (R1 = 2.2 kΩ, R2 = 47 kΩ), and AEC-Q101 qualification for automotive-grade reliability.

For engineers reviewing the NHUMB10 datasheet, NHUMB10 pinout, NHUMB10 application, or NHUMB10 equivalent, this device serves as a space- and cost-optimized replacement for discrete BC856-based driver stages in low-power logic interfacing, load switching, and level translation circuits where integrated base resistors reduce BOM count and layout complexity.

Technical Context

This dual PNP RET integrates two matched high-voltage PNP transistors with precision laser-trimmed on-chip base resistors-R1 (2.2 kΩ) connected between base and emitter, R2 (47 kΩ) between base and input-enabling direct logic-level drive without external bias components. Each transistor operates independently with open-base V_CEO = −80 V and I_O = −100 mA rating.

The device supports stable DC switching across −55 °C to +150 °C ambient, with thermal resistance R_th(j-a) = 358 K/W (per device on FR4 PCB) and junction temperature limit of 150 °C. Its off-state input voltage (V_I(off)) ranges from −595 mV to −500 mV, ensuring robust noise immunity in noisy digital environments.

Key Specifications

Pinout & Package

SOT363 (SC-88) 6-pin surface-mount plastic package with 0.65 mm pitch, 2.2 mm × 1.35 mm body size, and exposed pad-free construction. Designed for reflow and wave soldering per IPC-7095 guidelines.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PNP/PNP resistor-equipped transistor applications.

Compared with NHUMD10, NHUMB10 provides true dual-PNP functionality ideal for high-side switching and bus termination; versus BC856BDW1T1G, it trades minor h_FE headroom for significant reduction in component count, test points, and long-term field failure modes related to resistor solder joints.

Availability

NHUMB10 is available at Aetrix Electronics and suitable for automotive body electronics, industrial PLC input stages, consumer appliance power sequencing, and medical diagnostic equipment interface requiring stable component supply with AEC-Q101 assurance.

Supply support for NHUMB10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies-delivering high-performance, reliable, and scalable discrete, logic, and MOSFET solutions.

NHUMB10 belongs to Nexperia's resistor-equipped transistor (RET) product line, engineered specifically to replace discrete transistor-resistor combinations in cost- and space-constrained digital interface applications across automotive and industrial markets.

FAQ

What is the maximum allowable input voltage at I1 or I2 pins?

The absolute maximum input voltage at I1 or I2 is −20 V for NHUMB10, as specified in Table 6 (Limiting Values). This rating accounts for the internal R1–R2 divider and ensures safe operation even during transient overvoltage events on logic lines. Exceeding −20 V risks permanent damage to the base-emitter junction or integrated resistors.

Can NHUMB10 be used in linear amplifier configurations?

No-NHUMB10 is optimized for saturated switching operation, not linear amplification. Its h_FE is specified only at V_CE = −5 V and I_C = −10 mA, and its built-in resistors fix the base bias point. The datasheet does not characterize gain linearity, frequency response beyond f_T = 150 MHz, or distortion metrics required for analog amplification.

How does thermal performance differ between per-transistor and per-device power ratings?

The per-transistor P_tot is 235 mW, while the per-device rating is 350 mW. This reflects shared thermal path: simultaneous conduction in both transistors raises junction temperature faster than single-transistor operation. Derating follows Fig. 1-above 25 °C ambient, total device power must decrease linearly to maintain T_j ≤ 150 °C.

Is the marking code "6B%" laser-etched or molded?

The marking code "6B%" is laser-marked on the top surface of the SOT363 package, as confirmed by Nexperia's package documentation (Fig. 23) and marking table. The "%" placeholder denotes the manufacturing site code, which varies by fab location and is applied during final test and trim.