Nexperia USA Inc. PUMD13,115
- Part No.:
- PUMD13,115
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Bipolar Transistor Arrays, Pre-Biased
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
PUMD13,115.pdf
- Description:
- TRANS PREBIAS 1NPN 1PNP 6TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:38,155
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Product details
Overview
PUMD13 from Nexperia is a resistor-equipped double transistor (RET) integrating one NPN and one PNP bipolar junction transistor in a single SOT363-3 (SC-88) package, rated for 50 V VCEO, 100 mA output current per transistor, with built-in bias resistors R1 = 4.7 kΩ and R2 = 47 kΩ (R2/R1 = 10), used for compact digital logic interfacing and low-current peripheral control.
For engineers reviewing the PUMD13 datasheet, PUMD13 pinout, PUMD13 application, or PUMD13 equivalent, this device serves as a space- and BOM-optimized replacement for discrete NPN+PNP pairs in level-shifting, bus buffering, and IC input control circuits where input voltage thresholds (VI(on) = 0.9–1.3 V, VI(off) = 0.5–0.6 V) and guaranteed saturation (VCEsat ≤ 100 mV at IC = 5 mA) are critical.
Technical Context
The PUMD13 implements two independent RETs - TR1 (NPN) and TR2 (PNP) - each with monolithically integrated base bias resistors enabling direct TTL/CMOS-compatible drive without external components. The NPN section delivers hFE ≥ 100 at IC = 10 mA and fT = 230 MHz; the PNP section provides hFE ≥ 100 at IC = −10 mA and fT = 180 MHz.
Thermal design is constrained by a per-device Rth(j-a) of 417 K/W on FR4 PCB and a total power dissipation limit of 300 mW at Tamb ≤ 25 °C. Input voltage limits are asymmetric: +30 V/−5 V for TR1 (NPN), +5 V/−30 V for TR2 (PNP), reflecting complementary polarity operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCEO | 50 V - Maximum collector-emitter voltage before breakdown; supports rail-to-rail switching in 3.3 V and 5 V logic systems. |
| IO | 100 mA - Continuous DC output current per transistor; sufficient for driving LEDs, small relays, or logic inputs. |
| R1 | 4.7 kΩ - Integrated base input resistor; sets input current sensitivity and enables direct connection to CMOS outputs. |
| R2/R1 | 10 - Fixed bias ratio; ensures stable saturation and predictable turn-on behavior across temperature and process variation. |
| VCEsat | ≤ 100 mV at IC = 5 mA - Low saturation voltage minimizes power loss and ensures clean logic-level output swing. |
| hFE | ≥ 100 at IC = ±10 mA - Guaranteed DC current gain enables reliable switching with minimal base drive overhead. |
| fT | 230 MHz (TR1), 180 MHz (TR2) - Transition frequency confirms suitability for high-speed digital signal routing up to ~50 MHz. |
Pinout & Package
SOT363-3 (TSSOP6) plastic surface-mounted package with 6 leads, 0.65 mm pitch, and standard FR4 reflow footprint (2.2 × 1.35 mm body size). Pin 1 marked by index notch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | GND1 | Emiter connection for TR1 (NPN); common reference for first transistor's input/output path. |
| 2 | I1 | Base input for TR1 (NPN); driven through internal R1 resistor - accepts direct logic-level signals. |
| 3 | O2 | Collector output for TR2 (PNP); active-low switching node with −50 V VCBO rating. |
| 4 | GND2 | Emiter connection for TR2 (PNP); separate ground return for second transistor, enabling dual-rail operation. |
| 5 | I2 | Base input for TR2 (PNP); biased via same R1/R2 network but polarity-reversed for complementary control. |
| 6 | O1 | Collector output for TR1 (NPN); active-high switching node with +50 V VCBO rating. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated bias network | Monolithic R1 = 4.7 kΩ + R2 = 47 kΩ per transistor eliminates 4 external resistors and reduces layout area by >60%. |
| Dual-polarity RET pairing | NPN/PNP configuration enables push-pull output stages or bidirectional level translation without cross-coupling. |
| Guaranteed saturation | VCEsat ≤ 100 mV at IC = 5 mA ensures <1% voltage drop in logic-driven loads, preserving noise margins. |
| Input voltage compatibility | VI(on) = 0.9–1.3 V and VI(off) = 0.5–0.6 V match standard CMOS/TTL thresholds, eliminating need for external level shifters. |
| Thermal robustness | Rated for Tj ≤ 150 °C and Tamb = −65 to +150 °C; validated on standard FR4 PCB with 35 µm copper. |
Applications
| LED Driver Interface | Microcontroller GPIO Expander |
|---|---|
Use Scenario: Driving multiple status LEDs from a 3.3 V MCU with limited I/O current capability. IC Role / Device Role: Dual-transistor switch providing active-high (TR1) and active-low (TR2) LED control paths. Use Value: Eliminates need for discrete base resistors and separate NPN/PNP devices; reduces BOM count by 6 parts per channel. |
Use Scenario: Extending GPIO count for industrial sensor interface boards using 5 V tolerant logic. IC Role / Device Role: Level-shifting buffer between 3.3 V microcontroller and 5 V peripheral enable lines. Use Value: Built-in VI(on)/VI(off) thresholds ensure reliable switching across supply rails without external biasing. |
| Bus Signal Conditioning | Low-Power Logic Inverter Pair |
Use Scenario: Cleaning up noisy I²C or SPI bus signals in space-constrained IoT edge nodes. IC Role / Device Role: Active pull-up/pull-down driver pair replacing passive resistors to improve rise/fall times. Use Value: 230 MHz fT (TR1) supports clean 10 MHz clock edges; 100 mA drive handles capacitive loads up to 100 pF. |
Use Scenario: Implementing complementary inverters in battery-powered wearables requiring ultra-low quiescent current. IC Role / Device Role: Matched NPN/PNP pair delivering rail-to-rail inversion with sub-1 µA leakage (ICEO ≤ 5 µA at 150 °C). Use Value: Integrated R1/R2 ensures consistent switching thresholds across temperature, reducing calibration overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar resistor-equipped transistor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PUMB13 | PNP/PNP dual RET (no NPN section); identical R1/R2 values and SOT363-3 package. | Used when both outputs require active-low drive (e.g., dual enable lines), not complementary logic. | Select when circuit requires matched PNP outputs only - not a functional substitute for NPN/PNP pairing. |
| PUMH13 | NPN/NPN dual RET; same bias network and package, but no PNP transistor. | Applicable in push-pull drivers where both sides source current, or dual-sink configurations. | Choose only if both controlled loads are connected to VCC (not ground); cannot replicate PUMD13's bidirectional switching. |
Compared with PUMB13 and PUMH13, the PUMD13 uniquely delivers true complementary NPN/PNP switching in one package - essential for rail-to-rail signal inversion, half-bridge pre-driver stages, and mixed-voltage interface translation where polarity diversity is required.
Availability
PUMD13 is available at Aetrix Electronics and suitable for LED driver interfaces, microcontroller GPIO expansion, bus signal conditioning, and low-power logic inverter designs requiring stable component supply and long-term production continuity.
Supply support for PUMD13 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in automotive-grade and industrial MOSFETs, diodes, and RETs.
The PUMD13 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to reduce board space and assembly cost in digital interface and peripheral driver applications across consumer, industrial, and computing markets.
FAQ
What is the maximum operating temperature for PUMD13?
The PUMD13 is rated for junction temperature up to 150 °C and ambient temperature from −65 °C to +150 °C. Its thermal resistance is 417 K/W (per device on FR4 PCB), meaning at 25 °C ambient it can dissipate up to 300 mW before reaching max Tj. Derating is required above 25 °C per the published curve.
Can PUMD13 replace two separate SOT23 transistors in a design?
Yes - the PUMD13 integrates one NPN and one PNP transistor with matched bias networks into a single SOT363-3 package, directly replacing two discrete SOT23-3 devices plus four external base resistors. This reduces PCB area by ~40%, eliminates placement errors, and cuts pick-and-place cycle time.
How does the R2/R1 ratio affect switching performance?
The fixed R2/R1 = 10 ratio ensures optimal base biasing for saturation across process and temperature variations. It guarantees IC/IB ≥ 20 under typical conditions, resulting in VCEsat ≤ 100 mV and fast turn-off due to R2's discharge path - critical for clean digital transitions without external speed-up capacitors.
Is PUMD13 suitable for automotive applications?
No - the PUMD13 is not AEC-Q101 qualified and is explicitly designated for industrial and consumer use. Nexperia states in its legal disclaimers that non-automotive qualified products are unsuitable for safety-critical or life-support systems. Automotive designs require verified AEC-compliant alternatives like the PUMD13-Q series (if available) or equivalent qualified RETs.
PUMD13,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Transistor Type:
- 1 NPN, 1 PNP - Pre-Biased (Dual)
- Current - Collector (Ic) (Max):
- 100mA
- Voltage - Collector Emitter Breakdown (Max):
- 50V
- Resistor - Base (R1):
- 4.7kOhms
- Resistor - Emitter Base (R2):
- 47kOhms
- DC Current Gain (hFE) (Min) @ Ic, Vce:
- 100 @ 10mA, 5V
- Vce Saturation (Max) @ Ib, Ic:
- 100mV @ 250µA, 5mA
- Current - Collector Cutoff (Max):
- 1µA
- Frequency - Transition:
- -
- Power - Max:
- 300mW
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSSOP
PUMD13,115 FAQ
1.How can I place an order for PUMD13,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PUMD13,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PUMD13,115 reliable?
The price and inventory of PUMD13,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PUMD13,115 is usually 5 days.
3.What payment methods are accepted for PUMD13,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PUMD13,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PUMD13,115?
PUMD13,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PUMD13,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PUMD13,115?
For technical support, including PUMD13,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PUMD13,115 requirements.
6.How does Aetrix verify that PUMD13,115 is sourced from the original manufacturer or authorized distributors?
All PUMD13,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PUMD13,115 meets industry standards.
7.What is the process for return or replacement of PUMD13,115?
All PUMD13,115 units undergo pre-shipment inspection (PSI). If there is an issue with PUMD13,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PUMD13,115 part is unused and in its original packaging.
Return procedure for PUMD13,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PUMD13,115 Tags

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SMUN5311DW1T1G
onsemi

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Nexperia USA Inc.

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PUMD13,115
Nexperia USA Inc.
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