Nexperia USA Inc. PUMD3-QX

Overview

PUMD3-QX from Nexperia is a resistor-equipped double transistor (RET) integrating one NPN and one PNP bipolar junction transistor in a single SOT363-3 (TSSOP6) package, with built-in 10 kΩ input bias resistors (R1 = R2 = 10 kΩ), 50 V V_CEO, 100 mA output current per transistor, and AEC-Q101 qualification for automotive digital switching applications.

For engineers reviewing the PUMD3-QX datasheet, PUMD3-QX pinout, PUMD3-QX application, or PUMD3-QX equivalent, this device serves as a space- and BOM-optimized alternative to discrete BC847-Q/BC857-Q pairs in level-shifting, IC input control, and bidirectional load switching circuits requiring dual-polarity gain stages with integrated biasing.

Technical Context

The PUMD3-QX implements two monolithically integrated but electrically isolated transistors: TR1 (NPN) and TR2 (PNP), each with dedicated base bias networks (R1, R2) enabling direct logic-level drive without external resistors. Its complementary topology supports push-pull or polarity-reversal signal conditioning.

Each transistor operates independently under standard BJT DC biasing rules: TR1 delivers h_FE ≥ 30 at I_C = 5 mA, V_CE = 5 V; TR2 provides comparable gain with negative-polarity operation, and both exhibit V_CE(sat) ≤ 100 mV at I_C/I_B = 20, supporting low-loss switching up to 100 mA.

Key Specifications

Pinout & Package

SOT363-3 (TSSOP6) plastic surface-mounted package: 1.5 mm × 2.2 mm footprint, 0.65 mm pitch, 0.95 mm max height, optimized for automated reflow soldering on FR4 PCBs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-transistor switching applications.

Compared with PUMH11-Q and PUMB11-Q, the PUMD3-QX uniquely combines NPN and PNP gain stages in one package-enabling true complementary operation, reduced interconnect complexity, and smaller system footprint where bidirectional control or level translation is required.

Availability

PUMD3-QX is available at Aetrix Electronics and suitable for automotive body electronics, industrial PLC I/O modules, consumer appliance motor interfaces, and medical diagnostic signal gating requiring stable component supply and AEC-Q101 assurance.

Supply support for PUMD3-QX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable discrete and logic devices for automotive, industrial, and consumer markets.

The PUMD3-QX belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered to replace discrete BJT-resistor combinations in digital switching applications-reducing design complexity, improving manufacturing yield, and accelerating time-to-market for space-constrained electronics.

FAQ

What is the maximum operating junction temperature for PUMD3-QX?

The absolute maximum junction temperature (T_j) is 150 °C, validated per AEC-Q101 test conditions. At ambient temperatures up to 125 °C, derated power dissipation must be observed using the per-device thermal resistance curve (R_th(j-a) = 417 K/W on FR4), limiting continuous I_C to ~60 mA at T_amb = 105 °C.

Can PUMD3-QX replace BC847B and BC857B in existing designs without layout changes?

Yes-PUMD3-QX uses the same SOT363-3 footprint as BC847-Q/BC857-Q series, and its pinout maps GND1/I1/O1 to TR1 and GND2/I2/O2 to TR2, allowing direct substitution in dual-transistor layouts. However, verify that the integrated 10 kΩ bias resistors align with your drive strength and logic thresholds before drop-in replacement.

Does PUMD3-QX support AC-coupled or analog linear operation?

While primarily designed for digital switching, PUMD3-QX can operate in the linear region: TR1 exhibits f_T = 230 MHz and C_c = 2.5 pF; TR2 shows f_T = 180 MHz and C_c = 3 pF. These parameters support low-distortion analog gating up to ~10 MHz, provided V_CE remains within 1–10 V and I_C stays below 10 mA for stability.

How are the internal bias resistors tested and guaranteed?

Nexperia tests R1 and R2 per Table 8: R1 = 10 kΩ ±30%, R2 = 10 kΩ ±30%, measured at ±350 µA (TR1) and ∓450 µA (TR2) under defined voltage conditions. The R2/R1 ratio is guaranteed 0.8–1.2, ensuring predictable base current matching between transistors for consistent switching thresholds.