Nexperia USA Inc. PUMD2,115

Overview

PUMD2,115 from Nexperia is an NPN/PNP resistor-equipped double transistor (RET) in SOT363-3 (SC-88) package, rated for 50 V V_CEO, 100 mA output current per transistor, with built-in bias resistors R1 = R2 = 22 kΩ. It integrates complementary switching transistors for compact digital logic interfacing and low-current peripheral control in space-constrained PCBs.

For engineers reviewing the PUMD2,115 datasheet, PUMD2,115 pinout, PUMD2,115 application, or PUMD2,115 equivalent, this device serves as a drop-in replacement for discrete NPN+PNP pairs in level-shifting, bus buffering, and I/O conditioning circuits where bias resistor integration reduces layout complexity and BOM count.

Technical Context

The PUMD2,115 integrates one NPN (TR1) and one PNP (TR2) transistor sharing no internal connection between them-each has independent emitter-grounded configuration and dedicated base-input resistors. TR1 exhibits h_FE ≥ 60 at I_C = 5 mA, V_CE = 5 V; TR2 delivers comparable gain under negative-polarity conditions (V_CE = −5 V).

Both transistors feature matched 22 kΩ input bias resistors (R1/R2 ratio = 1.0 ± 0.2), enabling predictable turn-on thresholds (V_I(on) = 1.7–2.5 V for TR1; −1.7 to −2.5 V for TR2) and low leakage (I_CBO ≤ 100 nA, I_CEO ≤ 5 µA at T_j = 150 °C). Thermal resistance is 417 K/W (per device, FR4 PCB).

Key Specifications

Pinout & Package

SOT363-3 (TSSOP6) plastic surface-mounted package: 1.3 mm × 2.2 mm footprint, 0.65 mm pitch, 0.95 mm max height, designed for reflow soldering on FR4 PCBs with standard 0.5 mm pad width.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar resistor-equipped transistor applications.

Compared with PUMH1 and PUMB1, the PUMD2,115 uniquely provides true complementary NPN/PNP pairing in one package-enabling push-pull output stages, bidirectional level translation, and reduced interconnect in mixed-voltage systems without sacrificing board space or thermal performance.

Availability

PUMD2,115 is available at Aetrix Electronics and suitable for industrial automation interfaces, USB-C accessory designs, and IoT sensor node GPIO expansion requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant sourcing.

Supply support for PUMD2,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability essential semiconductors-including logic, discretes, MOSFETs, and ESD protection devices.

The PUMD2,115 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically for minimizing passive component count in digital interface and peripheral driver circuits across consumer, industrial, and computing applications.

FAQ

What is the maximum junction temperature and how does it affect continuous operation?

The absolute maximum junction temperature is 150 °C. At ambient temperatures up to 85 °C, the device sustains full 100 mA per transistor with derated power dissipation (300 mW total device limit). Thermal resistance of 417 K/W (junction-to-ambient, FR4 PCB) means 100 mA switching at 5 V drop generates ~500 mW worst-case power, requiring careful thermal layout or reduced duty cycle above 60 °C ambient.

Can PUMD2,115 be used in linear amplifier configurations?

No-it is optimized for switching operation only. The datasheet specifies no small-signal parameters (e.g., g_m, r_π) or linearity metrics. Its built-in resistors fix base biasing for digital on/off states, and h_FE variation across I_C (Fig. 3 and Fig. 9) confirms nonlinear gain behavior unsuitable for analog amplification.

How are the internal resistors R1 and R2 connected relative to transistor terminals?

R1 connects between Pin 2 (I1) and Pin 1 (GND1), biasing the base of TR1 (NPN). R2 connects between Pin 5 (I2) and Pin 4 (GND2), biasing the base of TR2 (PNP). Neither resistor shares nodes across transistors-ensuring independent control and preventing cross-talk in mixed-polarity operation.

Is there any difference between PUMD2 and PUMD2,115 in electrical performance or packaging?

No. PUMD2,115 is the orderable part number for the PUMD2 device in tape-and-reel packaging (10,000 units/reel) per Table 3. All electrical characteristics, pinout, thermal data, and package dimensions match the PUMD2 base designation-",115" denotes packaging variant only, not a functional revision.