Nexperia USA Inc. PBLS4004D,115

Overview

PBLS4004D,115 from NXP Semiconductors is a dual-function SOT457-packaged discrete device integrating a 40 V PNP low-V_CEsat Breakthrough In Small Signal (BISS) transistor (TR1) and a 50 V NPN resistor-equipped transistor (RET) (TR2). It delivers R_CEsat = 240–340 mΩ at I_C = −500 mA, V_I(on) = 1.7–2.5 V, and R₁ = 15.4–28.6 kΩ, enabling high-side load switching in portable battery-powered systems.

For engineers reviewing the PBLS4004D,115 datasheet, PBLS4004D,115 pinout, PBLS4004D,115 application, or PBLS4004D,115 equivalent, this dual-transistor solution supports space-constrained designs requiring low-threshold drive, reduced component count, and stable high-side switching for LED backlights, battery chargers, and supply-line control.

Technical Context

The PBLS4004D integrates two functionally independent transistors on one die: TR1 operates as a PNP BISS switch with V_CEO = −40 V, I_C = −1 A, and ultra-low saturation resistance; TR2 functions as an NPN RET with integrated R₁/R₂ bias network (R₂/R₁ = 0.8–1.2), eliminating external base resistors. Both share thermal coupling but retain separate electrical domains.

TR1's low V_BEsat (−1.1 V at I_C = −1 A) and TR2's defined VI(on)/VI(off) thresholds (1.7–2.5 V / 0.8–1.1 V) enable direct microcontroller GPIO interfacing without level-shifting. The device is characterized for ceramic (Al₂O₃) and FR4 PCB mounting, with R_th(j-a) as low as 210 K/W under optimized layout.

Key Specifications

Pinout & Package

SOT457 (SC-74) 6-lead surface-mount plastic package, 3.0 mm × 2.5 mm footprint, 1.3 mm height, with standard taping (4 mm pitch, 8 mm reel) per ordering code suffix -115.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-transistor load-switch applications.

Compared with NSBC114EDXV6T1G and DMN3028LSD-13, PBLS4004D,115 uniquely combines high-side PNP switching and logic-compatible NPN RET in one package-enabling compact, self-contained load switching without external biasing or level translation, ideal for space- and BOM-constrained portable designs.

Availability

PBLS4004D,115 is available at Aetrix Electronics and suitable for LED backlight control, battery charger enable circuits, and high-side supply switching requiring stable component supply, consistent parametric performance, and long-term industrial availability.

Supply support for PBLS4004D,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer applications.

PBLS4004D belongs to NXP's BISS+RET family, designed specifically for miniaturized, low-power load-switching in portable electronics where integration, low drive power, and thermal efficiency are critical.

FAQ

What is the maximum continuous collector current for TR1 at 25 °C ambient?

The maximum continuous collector current for TR1 is −1 A when mounted on a ceramic Al₂O₃ PCB with standard footprint (Table 1, Quick Reference Data). Derating applies above 25 °C: at 85 °C ambient, max I_C drops to approximately −0.6 A per Figure 1 power derating curve.

Can TR2 be used independently while TR1 remains unconnected?

Yes - TR1 and TR2 are electrically isolated except for shared substrate thermal coupling. TR2 operates fully independently: its input (pin 5), output (pin 3), and emitter (pin 4) form a complete NPN RET circuit. Pin 1 (TR1 emitter), pin 2 (TR1 base), and pin 6 (TR1 collector) may be left floating or grounded without affecting TR2 function.

What is the recommended PCB layout for optimal thermal performance?

For best thermal performance, mount PBLS4004D,115 on a ceramic Al₂O₃ PCB (R_th(j-a) = 210 K/W) or use FR4 with 1 cm² copper pour under pin 6 (TR1 collector) to achieve R_th(j-a) = 236 K/W. Avoid thermal isolation of pin 6; connect it directly to internal ground or power planes using multiple vias.

Does PBLS4004D,115 support PWM switching at frequencies above 10 kHz?

Yes - TR1's f_T = 150 MHz and low C_c = 12 pF allow clean switching up to at least 100 kHz. Measured V_CEsat transient response (Fig 9–10) shows sub-µs turn-on/off times. For >50 kHz PWM, ensure gate drive to TR1 base (pin 2) has ≤100 Ω series resistance to prevent ringing.