Nexperia USA Inc. PEMD12,315

Overview

PEMD12 from Nexperia is an NPN/PNP resistor-equipped double transistor (RET) in SOT666 package, integrating two complementary bias-resistor-transistors - TR1 (NPN) and TR2 (PNP) - each rated for 50 V V_CEO, 100 mA I_O, with matched R1 = R2 = 47 kΩ built-in bias resistors. It serves as a compact, dual-polarity digital switching element for level translation and low-current drive in space-constrained logic interface circuits.

For engineers reviewing the PEMD12 datasheet, PEMD12 pinout, PEMD12 application, or PEMD12 equivalent, this device is selected for simplified digital output buffering, IC input control, and replacement of discrete NPN+PNP pairs where board area, BOM count, and pick-and-place cost reduction are critical design objectives.

Technical Context

The PEMD12 integrates two monolithically isolated transistors on a single die: TR1 is an NPN transistor with base biased via R1–R2 network to ground, while TR2 is a PNP transistor with its own identical R1–R2 network referenced to its emitter (GND2). Both transistors share no internal connection beyond common package substrate, enabling independent operation with polarity-separated signal paths.

Each transistor exhibits h_FE ≥ 80 at I_C = 5 mA, V_CE = 5 V (NPN) or −5 V (PNP), and V_CE(sat) ≤ 150 mV at I_C = 10 mA / I_B = 0.5 mA (NPN) or corresponding negative conditions (PNP), supporting reliable saturation switching in 3.3 V and 5 V logic domains.

Key Specifications

Pinout & Package

SOT666 plastic surface-mount package: 6-pin, 0.5 mm pitch, 1.6 mm × 1.2 mm × 0.55 mm body height; ultra-flat lead profile optimized for automated assembly and high-density routing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar resistor-equipped transistor applications.

Compared with PEMH2 and PEMB2, the PEMD12 uniquely delivers true complementary switching in one device - enabling single-package solutions for bidirectional signal control, level translation, and power-gated sensor interfaces that neither alternative can replicate without added discretes.

Availability

PEMD12 is available at Aetrix Electronics and suitable for LED driver interfaces, microcontroller GPIO expansion, logic-level translation, and low-power sensor interface applications requiring stable component supply, long-term manufacturability, and RoHS-compliant SMT assembly.

Supply support for PEMD12 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies - delivering high-performance, reliable, and scalable components for automotive, industrial, and consumer electronics.

The PEMD12 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to reduce bill-of-materials complexity and PCB real estate in digital interface and low-power switching applications.

FAQ

What is the maximum continuous current per transistor in the PEMD12?

The PEMD12 supports a maximum continuous output current of 100 mA per transistor under T_amb ≤ 25 °C with FR4 PCB mounting. Derating applies above 25 °C ambient: total device power dissipation drops linearly to 0 mW at 150 °C junction temperature, per the 417 K/W thermal resistance specification.

Can the PEMD12 be used with 1.8 V logic inputs?

Yes - the NPN section (TR1) turns on with V_I(on) = 1.6 V (typical) at I_C = 2 mA, and the PNP section (TR2) activates with V_I(on) = −1.6 V (typical) under same conditions. This allows direct interfacing with 1.8 V CMOS outputs without level shifting, provided input current remains within ±110 μA limits per base terminal.

Is there electrical isolation between the NPN and PNP sections?

No internal galvanic isolation exists - both transistors share the same silicon die and substrate. However, their emitter terminals (GND1 and GND2) are electrically separate pins, enabling independent grounding or referencing to different rails. No current flows between TR1 and TR2 except through external circuitry.

What is the marking code for the PEMD12 on the SOT666 package?

The PEMD12 is marked with the code "D2" on the top surface of the SOT666 package, as specified in Table 4 of the official Nexperia data sheet dated 28 December 2022. This two-character laser marking is visible under 20× magnification and conforms to JEDEC standards for SMT identification.