Nexperia USA Inc. PEMD13,115

Overview

PEMD13 from Nexperia is a resistor-equipped double transistor (RET) integrating one NPN and one PNP bipolar junction transistor in a single SOT666 package, with built-in bias resistors R1 = 4.7 kΩ and R2 = 47 kΩ, rated for 50 V V_CEO, 100 mA output current per transistor, and operating across –65 °C to +150 °C ambient temperature - used for bidirectional digital signal interfacing in space-constrained logic-level translation circuits.

For engineers reviewing the PEMD13 datasheet, PEMD13 pinout, PEMD13 application, or PEMD13 equivalent, this device serves as a compact, bias-resistor-integrated solution for replacing discrete NPN+PNP pairs in low-current peripheral drivers, IC input control, and level-shifting nodes where PCB area and BOM count reduction are critical.

Technical Context

The PEMD13 implements two independent transistors - TR1 (NPN) and TR2 (PNP) - each with dedicated base biasing networks (R1 and R2), enabling direct TTL/CMOS-compatible switching without external resistors. The NPN section features h_FE ≥ 100 at I_C = 10 mA and V_CE = 5 V, while the PNP section delivers comparable gain under negative-polarity conditions.

Both transistors share thermal coupling within the ultra-small SOT666 package (1.6 mm × 1.2 mm × 0.55 mm), with per-device total power dissipation rated at 300 mW at T_amb ≤ 25 °C and junction temperature limited to 150 °C. Input voltage thresholds are specified: VI(on) = 0.9–1.3 V (TR1), VI(off) = 0.5–0.6 V (TR1), supporting robust noise margin in digital control paths.

Key Specifications

Pinout & Package

SOT666 plastic surface-mount package: 6-lead, 0.5 mm pitch, 1.6 mm × 1.2 mm × 0.55 mm body height, designed for reflow soldering only on FR4 PCBs with single-sided copper.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar resistor-equipped transistor applications.

Compared with PEMH13 and PEMB13, the PEMD13 uniquely provides true complementary NPN/PNP pairing in one package - enabling push-pull output stages, bidirectional bus control, and compact H-bridge pre-driver functions not achievable with same-polarity RETs.

Availability

PEMD13 is available at Aetrix Electronics and suitable for LED driver interfaces, microcontroller GPIO expansion, logic-level translation, and low-power sensor interface applications requiring stable component supply and long-term production continuity.

Supply support for PEMD13 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, discrete, and MOSFET devices, with manufacturing rooted in process innovation and automotive-grade quality systems.

The PEMD13 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to reduce design complexity and board space in digital interface and peripheral driver applications across consumer, industrial, and computing markets.

FAQ

What is the maximum allowable continuous current per transistor in the PEMD13?

The PEMD13 supports a maximum continuous output current of 100 mA per transistor (TR1 and TR2 individually), as confirmed in the Quick Reference Data and Limiting Values tables. This rating applies under T_amb ≤ 25 °C with proper PCB thermal relief; derating is required above 25 °C per the 417 K/W junction-to-ambient thermal resistance curve.

Can the GND1 and GND2 pins be connected together in a circuit?

Yes, GND1 and GND2 may be externally connected to a common ground plane, but they are not internally shorted. Doing so simplifies layout and enables shared reference for bidirectional signal paths - however, isolation should be maintained if TR1 and TR2 drive loads referenced to different supply domains (e.g., isolated 5 V and 24 V rails).

Does the PEMD13 support 1.8 V logic input levels reliably?

Yes - the TR1 NPN section has VI(on) = 0.9–1.3 V and VI(off) = 0.5–0.6 V, providing a 300–400 mV noise margin at 1.8 V logic high. Test data shows stable turn-on down to 0.9 V at 25 °C, making it compatible with 1.8 V CMOS outputs without level-shifting circuitry.

Is reflow soldering the only recommended assembly method for the SOT666 package?

Yes - the datasheet explicitly states that reflow soldering is the only recommended method for PEMD13. Hand soldering or wave soldering is not qualified due to thermal stress risks on the ultra-thin leadframe and internal die attach; the package outline and solder land pattern in Figure 18 are optimized exclusively for lead-free reflow profiles.