NXP Semiconductors PEMD19,115

Overview

PEMD19 from Nexperia is a dual NPN/PNP resistor-equipped transistor (RET) in SOT666 package, integrating one NPN and one PNP transistor with built-in 22 kΩ input bias resistors (R1) and open R2 terminals. It delivers 100 mA DC output current per transistor, 50 V VCEO rating, and operates across −65 °C to +150 °C ambient range. Used for low-current digital signal inversion and IC input control in space-constrained logic interfaces.

For engineers reviewing the PEMD19 datasheet, PEMD19 pinout, PEMD19 application, or PEMD19 equivalent, this page provides verified pin functions, thermal resistance (416 K/W per device), bias resistor tolerance (±29%), dual-transistor timing coordination, and direct replacement guidance against PEMB19 and PEMH19.

Technical Context

The PEMD19 integrates two complementary bipolar transistors-TR1 (NPN) and TR2 (PNP)-on a single die with dedicated base bias networks. Each transistor has an independently accessible 22 kΩ input resistor (R1) and no second bias resistor (R2 = open), enabling flexible external pull-up/down configuration.

Its SOT666 package supports reflow-only soldering on FR4 PCBs and delivers 300 mW total power dissipation at Tamb ≤ 25 °C. The device exhibits 100–500 hFE at IC = 1 mA (VCE = 5 V), 150 mV VCEsat at IC = 10 mA/IB = 0.5 mA, and junction-to-ambient thermal resistance of 416 K/W per device.

Key Specifications

Pinout & Package

SOT666 plastic surface-mounted package (6-lead), 1.7 mm × 1.3 mm footprint, 0.65 mm pitch, 0.5 mm height; optimized for high-density routing and automated placement.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual RET applications.

Compared with PEMB19 and PEMH19, PEMD19 uniquely balances complementary functionality, 22 kΩ bias for 3.3 V logic compatibility, and 100 mA drive-making it optimal for mixed-signal interface consolidation where polarity diversity and drive strength are both essential.

Availability

PEMD19 is available at Aetrix Electronics and suitable for LED indicator driver, microcontroller GPIO expander, and digital logic level shifter applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for PEMD19 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global leader in discrete, logic, and PowerMOS semiconductors, spun off from NXP's Standard Products division in 2017 and headquartered in Nijmegen, Netherlands.

The PEMD19 belongs to Nexperia's resistor-equipped transistor (RET) product line, engineered specifically for reducing component count and simplifying digital interface design in automotive, industrial, and consumer electronics.

FAQ

What is the function of the open R2 terminal in PEMD19?

The R2 terminal is unconnected internally, allowing designers to add an external resistor between base and emitter (or collector) for custom biasing-such as improving turn-off speed, adding hysteresis, or configuring Darlington-like gain. This differs from fixed-R2 RETs and enables application-specific optimization without changing the base part number.

Can PEMD19 replace discrete transistor + resistor combinations in existing designs?

Yes-PEMD19 replaces one NPN, one PNP, and two 22 kΩ base resistors in a single SOT666 footprint. Pin mapping matches standard dual-transistor layouts: pins 1/2/6 form TR1 (NPN), pins 3/4/5 form TR2 (PNP). No layout redesign is needed if the PCB pad pattern aligns with SOT666 mechanical dimensions (1.7 mm × 1.3 mm, 0.65 mm pitch).

What is the maximum allowable continuous power dissipation per transistor?

Each transistor is rated for 200 mW at Tamb ≤ 25 °C (per limiting values table), but the device-level rating is 300 mW total. Therefore, simultaneous full-load operation of both transistors requires derating: e.g., 150 mW per transistor at 25 °C ambient, or ambient reduction to ≤15 °C for sustained 200 mW per side.

Does PEMD19 support 1.8 V logic input levels?

No-its 22 kΩ R1 yields ~82 µA base current at 1.8 V, below the 100 µA minimum needed for guaranteed hFE ≥100. It is specified for 3.3 V and 5 V logic families. For 1.8 V systems, use PEMH19 (47 kΩ R1) or add an external level-shifting buffer.