Nexperia USA Inc. PEMH4,115

Overview

PEMH4,115 from Nexperia is a dual NPN resistor-equipped transistor (RET) in SOT666 package, integrating two independent NPN transistors each with a 10 kΩ built-in base bias resistor (R1) and open R2. It delivers 50 V V_CEO, 100 mA output current per transistor, and operates across –65 °C to +150 °C ambient. It serves as a compact, low-component-count driver for digital logic interfaces and IC input control in space-constrained consumer and industrial PCBs.

For engineers reviewing the PEMH4,115 datasheet, PEMH4,115 pinout, PEMH4,115 application, or PEMH4,115 equivalent, key selection criteria include verified dual-NPN RET functionality, confirmed 10 kΩ input bias resistor value, validated SOT666 6-pin layout, thermal derating on FR4 PCB, and compatibility with reflow-only assembly.

Technical Context

The PEMH4,115 integrates two electrically isolated NPN transistors sharing no internal connection between channels-each features a dedicated 10 kΩ base-input resistor (R1) and no second bias resistor (R2 = open). Its design eliminates external base resistors while preserving full control over base drive current via I1/I2 pins.

It operates under standard digital logic voltage levels (V_EB ≤ 5 V, V_CE ≤ 50 V), supports DC current gain (h_FE) ≥ 200 at I_C = 1 mA, and maintains V_CE(sat) ≤ 150 mV at I_C = 10 mA / I_B = 0.5 mA-enabling reliable low-power switching in 3.3 V/5 V systems.

Key Specifications

Pinout & Package

SOT666 plastic surface-mount package: 6-lead, 0.5 mm pitch, 1.6 mm × 1.2 mm × 0.55 mm body height, designed exclusively for reflow soldering on FR4 PCBs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-NPN RET applications.

Compared with PEMD4,115 and EMH4,115, the PEMH4,115 uniquely delivers dual-NPN topology in the smallest industry-standard RET package-making it optimal for miniaturized digital I/O expansion where both channels must sink current and board area is constrained below 2 mm².

Availability

PEMH4,115 is available at Aetrix Electronics and suitable for LED indicator driving, microcontroller GPIO expansion, digital logic input conditioning, and low-power sensor interface applications requiring stable component supply and long-term industrial availability.

Supply support for PEMH4,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET devices optimized for reliability and manufacturability.

The PEMH4,115 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to reduce component count and simplify digital interface design in cost- and space-sensitive consumer, computing, and industrial electronics.

FAQ

What is the function of Pin 3 (O2) and Pin 6 (O1) on the PEMH4,115?

Pin 3 (O2) is the collector output of the second NPN transistor (TR2), while Pin 6 (O1) is the collector output of the first NPN transistor (TR1). Both operate as independent switched outputs capable of sinking up to 100 mA each. Neither output is internally connected-enabling fully isolated dual-channel switching without shared load paths or crosstalk.

Can the PEMH4,115 be used with 1.8 V logic inputs?

Yes-the 10 kΩ internal R1 resistor allows functional operation down to 1.8 V: at that voltage, base current is ~180 µA, sufficient to achieve h_FE-supported saturation for loads ≤ 20 mA. However, V_CE(sat) increases slightly versus 3.3 V operation, and full 100 mA output requires ≥2.5 V input to ensure adequate base drive.

Is hand soldering supported for the PEMH4,115 SOT666 package?

No-Nexperia explicitly specifies reflow soldering as the only recommended method. The SOT666's 0.5 mm pitch, thermal pad design, and thin profile make hand soldering unreliable and prone to bridging or insufficient wetting. Use JEDEC-compliant reflow profiles with peak temperatures ≤ 260 °C and controlled ramp rates.

How does the PEMH4,115 handle thermal dissipation in continuous operation?

At 25 °C ambient, the device supports 300 mW total power dissipation (150 mW per transistor). With R_th(j-a) = 416 K/W, junction temperature rises ~125 °C above ambient at full load-requiring derating above 25 °C. For continuous 100 mA per channel, ambient must stay ≤ 25 °C or power must be reduced per the published derating curve (e.g., 100 mW per transistor at 75 °C ambient).