Nexperia USA Inc. PQMD13Z

Overview

PQMD13 from Nexperia is an NPN/PNP dual resistor-equipped transistor (RET) in a DFN1010B-6 (SOT1216) package, integrating built-in bias resistors R1 = 4.7 kΩ and R2 = 47 kΩ. It delivers 100 mA output current per transistor, supports ±50 V collector-emitter voltage, and is AEC-Q101 qualified for automotive use in low-current peripheral driver circuits.

For engineers reviewing the PQMD13 datasheet, PQMD13 pinout, PQMD13 application, or PQMD13 equivalent, this device serves as a space-optimized, component-count-reducing replacement for discrete NPN+PNP transistor pairs with external biasing in digital control interfaces and IC input conditioning circuits.

Technical Context

The PQMD13 integrates two monolithic transistors - one NPN and one PNP - each with dedicated on-die base bias networks (R1 and R2). The NPN transistor features hFE ≥ 100 at IC = 10 mA, VCE = 5 V, and VCEsat ≤ 100 mV at IC = 5 mA/IB = 0.25 mA; the PNP exhibits symmetric limiting values including VCEO = –50 V and comparable saturation performance.

Its DFN1010B-6 package enables ultra-thin mounting (0.37 mm height) with thermal resistance Rth(j-a) = 357 K/W (per device on FR4 PCB), supporting operation from –55 °C to +150 °C ambient and junction temperatures up to 150 °C under defined power dissipation limits.

Key Specifications

Pinout & Package

DFN1010B-6 (SOT1216) package: 1.1 mm × 1.0 mm × 0.37 mm body, 0.35 mm pitch, leadless thermal-enhanced ultra-thin outline.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual RET applications.

Compared with NX3020NA and PQMH13, PQMD13 uniquely provides integrated NPN+PNP functionality in one die, enabling true complementary switching without layout compromises or timing skew between channels.

Availability

PQMD13 is available at Aetrix Electronics and suitable for automotive body control modules, industrial PLC digital outputs, and mobile power sequencing applications requiring stable component supply and AEC-Q101 compliance.

Supply support for PQMD13 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable discrete, logic, and MOSFET devices.

The PQMD13 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered to simplify digital interface design in space-constrained, high-reliability applications across automotive and industrial markets.

FAQ

What is the maximum operating temperature for PQMD13?

The PQMD13 supports ambient temperatures from –55 °C to +150 °C and junction temperatures up to 150 °C. Its thermal resistance (Rth(j-a) = 357 K/W on FR4) allows sustained operation at full 100 mA load within this range when mounted per recommended footprint and copper pour guidelines.

Can PQMD13 replace discrete BC847/BC857 transistor pairs?

Yes - PQMD13 replaces one NPN (e.g., BC847) and one PNP (e.g., BC857) plus four external bias resistors. Its integrated R1 = 4.7 kΩ and R2 = 47 kΩ network delivers equivalent DC biasing behavior, with verified VCEsat ≤ 100 mV and hFE ≥ 100 under standard test conditions.

Is PQMD13 pin-compatible with other DFN1010B-6 RETs like PQMH13?

Yes - PQMD13 shares identical DFN1010B-6 (SOT1216) mechanical dimensions, pad layout, and pin numbering with PQMH13. However, internal connectivity differs: PQMD13 assigns pins 1/2/6 to TR1 (NPN) and 3/4/5 to TR2 (PNP), whereas PQMH13 configures all six pins for two NPNs.

Does PQMD13 support 1.8 V logic-level drive?

No - VI(on) is specified at 0.9–1.3 V (typ/max) for reliable NPN turn-on, but VI(off) is 0.5–0.6 V (typ/max). At 1.8 V, the device operates in linear region with elevated VCEsat and reduced noise margin; it is validated for 3.3 V and 5 V GPIO interfaces per datasheet test conditions.