Nexperia USA Inc. PQMD2Z

Overview

PQMD2 from Nexperia is an NPN/PNP dual resistor-equipped transistor (RET) in a DFN1010B-6 (SOT1216) package, integrating two matched bias networks (R1 = R2 = 22 kΩ) for simplified digital switching. It delivers 100 mA per transistor, supports ±50 V collector-emitter voltage, and is AEC-Q101 qualified for automotive signal conditioning and level translation.

For engineers reviewing the PQMD2 datasheet, PQMD2 pinout, PQMD2 application, or PQMD2 equivalent, this device serves as a space-optimized, bias-resistor-integrated replacement for discrete NPN+PNP pairs in low-current peripheral drivers, IC input control, and mobile interface logic-where board area, pick-and-place cost, and thermal performance are critical selection criteria.

Technical Context

The PQMD2 integrates two complementary RETs-TR1 (NPN) and TR2 (PNP)-each with built-in base bias resistors (R1 = 22 kΩ, R2 = 22 kΩ) enabling direct logic-level drive without external components. The R2/R1 ratio of 1.0 ensures matched on/off thresholds across both transistors.

It operates over −55 °C to +150 °C ambient, with per-transistor power dissipation up to 230 mW and per-device total dissipation up to 350 mW on FR4 PCB. Its ultra-thin 0.37 mm profile and 1.05 mm × 1.05 mm footprint support high-density portable and automotive PCB layouts.

Key Specifications

Pinout & Package

DFN1010B-6 (SOT1216) is a 6-terminal, leadless, ultra-thin surface-mount plastic package with exposed thermal pad (not electrically connected), measuring 1.05 mm × 1.05 mm × 0.37 mm height. Pin 1 is marked by a beveled corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual RET applications.

Compared with NSVD2T2220Z and EMD2P50R, PQMD2 offers matched 1:1 bias networks ideal for symmetric push-pull operation, smallest footprint among dual RETs, and lowest assembly cost-making it optimal for high-volume, space-constrained automotive and mobile designs where design-in simplicity and qualification assurance are prioritized.

Availability

PQMD2 is available at Aetrix Electronics and suitable for automotive door modules, smartphone power sequencing, industrial PLC input conditioning, and wearable sensor hub designs requiring stable component supply, AEC-Q101 traceability, and ultra-compact packaging.

Supply support for PQMD2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-performance, reliable standard products including logic, discretes, MOSFETs, and analog ICs, serving automotive, industrial, and consumer markets.

The PQMD2 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to replace discrete transistor-resistor combinations in digital interface and level-shifting applications-reducing design time, PCB area, and manufacturing cost.

FAQ

What is the maximum allowable continuous current per transistor in PQMD2?

The PQMD2 supports a continuous output current (I_O) of 100 mA per transistor under normal operating conditions, as specified in the Quick Reference Data table. This rating assumes T_amb ≤ 25 °C and proper PCB thermal relief; derating applies above 25 °C per the per-device power derating curve (350 mW → 0 at 125 °C).

Can PQMD2 be used with 1.8 V logic inputs?

No-PQMD2's VI(on) is specified at 1.7 V (min) for NPN and −1.7 V (max) for PNP at I_C = 5 mA, making reliable turn-on marginal below 2.5 V. It is optimized for 3.3 V and 5 V CMOS/TTL systems; for 1.8 V interfaces, a level shifter or logic-family-matched RET like PBSS4041T must be used.

Is the thermal pad on the DFN1010B-6 package electrically connected?

No-the DFN1010B-6 package has an exposed thermal pad that is not electrically connected to any internal die structure or terminal. It is intended solely for thermal conduction to the PCB copper pour and must be soldered to a non-functional thermal land per Nexperia's recommended footprint (Fig. 21).

How does PQMD2 handle reverse polarity on its PNP section?

The PNP transistor (TR2) is rated for V_CEO = −50 V and V_EBO = −10 V, allowing safe operation with negative emitter-base and collector-emitter voltages. Its VI(off) is −0.8 V (typ), ensuring reliable cutoff when driven with negative logic swings up to −10 V, as confirmed in Figures 14–15 of the datasheet.