Nexperia USA Inc. PUMB1,115

Overview

PUMB1 from Nexperia is a dual PNP resistor-equipped transistor (RET) in SOT363 (SC-88) package, integrating two matched PNP transistors with built-in 22 kΩ input bias resistors (R1) and 22 kΩ feedback resistors (R2), rated for −50 V V_CEO, −100 mA output current per transistor, and AEC-Q101 qualified for automotive signal conditioning and digital logic interface applications.

For engineers reviewing the PUMB1 datasheet, PUMB1 pinout, PUMB1 application, or PUMB1 equivalent, this device serves as a space- and BOM-optimized replacement for discrete PNP pairs in level-shifting, bus buffering, and low-power peripheral driver circuits where bias resistor matching, thermal stability, and reflow-compatible ultra-small packaging are critical.

Technical Context

The PUMB1 integrates two independent PNP transistors sharing no internal connection between collector-emitter paths, each with dedicated base-input resistors (R1 = 22 kΩ ±30%) and emitter-feedback resistors (R2 = 22 kΩ ±30%), enabling direct TTL/CMOS-compatible switching without external bias networks. Its R2/R1 ratio of 0.8–1.2 ensures consistent turn-on/off thresholds across temperature.

Designed for operation at ambient temperatures from −65 °C to +150 °C, it delivers h_FE ≥60 at I_C = −5 mA and V_CE = −5 V, with V_CE(sat) ≤ −150 mV at I_C = −10 mA/I_B = −0.5 mA, supporting reliable saturation in low-voltage digital control paths.

Key Specifications

Pinout & Package

SOT363 (SC-88) 6-pin ultra-small flat-lead surface-mount package, 2.0 mm × 1.25 mm footprint, 0.65 mm pitch, with exposed pad not electrically connected.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual PNP resistor-equipped transistor applications.

Compared with NSVD2P0233MUTBG and EMZ6T2R, PUMB1 uniquely delivers matched dual-PNP topology with 22 kΩ biasing, AEC-Q101 qualification, and SOT363 pinout-making it optimal for space-constrained automotive and industrial digital interface designs requiring identical channel behavior.

Availability

PUMB1 is available at Aetrix Electronics and suitable for automotive body control modules, industrial PLC input stages, and consumer appliance keypad interfaces requiring stable component supply, long-term lifecycle support, and AEC-Q101-compliant sourcing.

Supply support for PUMB1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global leader in discrete, logic, and PowerMOS semiconductors, spun off from NXP in 2017, with engineering centers across Europe, Asia, and the Americas.

The PUMB1 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, designed specifically to replace discrete transistor-resistor combinations in automotive, industrial, and consumer digital signal conditioning applications.

FAQ

What is the maximum junction temperature for continuous operation of PUMB1?

The absolute maximum junction temperature (T_j) for PUMB1 is 150 °C, verified per IEC 60134 limiting values. Operation above this threshold risks permanent degradation of h_FE and leakage current. Derating begins at T_amb > 25 °C per the 417 K/W per-device R_th(j-a) curve in Figure 1, requiring thermal pads or copper pour for sustained −100 mA loads above 85 °C ambient.

Can PUMB1 be used in bidirectional signal paths such as I²C bus pull-ups?

No-PUMB1 is a unidirectional PNP sink-only device with fixed emitter-ground connection and no inherent bidirectional conduction path. Its architecture lacks the symmetrical structure required for I²C open-drain arbitration; use dedicated bidirectional level translators like NXH010P120L2 or discrete MOSFET solutions instead.

Is the R2/R1 ratio guaranteed across temperature and process variation?

Yes-the R2/R1 ratio is specified as 0.8 to 1.2 over full operating temperature (−65 °C to +150 °C) and process lot, derived from matched polysilicon resistor fabrication. This ensures stable VI(on) and VI(off) thresholds (−1.7 V to −2.5 V and −0.8 V to −1.1 V respectively) regardless of thermal drift or wafer-to-wafer variation.

Does PUMB1 require external decoupling capacitors for stable switching?

No external decoupling is required for basic digital switching, as the integrated R1/R2 network provides inherent filtering. However, for high-speed edges (>5 MHz) or noisy environments, a 100 nF ceramic capacitor placed between Pin 1 (GND TR1) and Pin 4 (GND TR2) reduces common-mode crosstalk and improves transient immunity per Figure 4–7 characterization data.