Nexperia USA Inc. PUMB11/ZLX

Overview

PUMB11 from Nexperia is a PNP/PNP resistor-equipped double transistor (RET) in SOT363-3 (SC-88) package, rated for −50 V V_CEO, −100 mA output current per transistor, with integrated R1 = 10 kΩ and R2 = 10 kΩ bias resistors; used for low-current digital switching and IC input control in space-constrained consumer and industrial logic interfaces.

For engineers reviewing the PUMB11 datasheet, PUMB11 pinout, PUMB11 application, or PUMB11 equivalent, this device serves as a dual-channel, surface-mount discrete solution optimized for reducing component count in 3.3 V/5 V logic-level peripheral driver circuits where thermal budget and PCB area are constrained.

Technical Context

The PUMB11 integrates two matched PNP transistors with monolithically embedded base bias networks-each channel includes independent 10 kΩ input resistors (R1) and 10 kΩ feedback resistors (R2), yielding R2/R1 = 1.0 ±20%. It operates with open-base V_CEO = −50 V and supports continuous I_O = −100 mA per transistor at T_amb ≤ 25 °C.

Thermal performance is defined for FR4 PCB mounting: per-device P_tot = 300 mW at 25 °C, derating linearly to zero at 150 °C; R_th(j-a) = 417 K/W. Device junction temperature must not exceed 150 °C under steady-state operation.

Key Specifications

Pinout & Package

SOT363-3 (SC-88 / TSSOP6) plastic surface-mounted package: 2.2 mm × 1.35 mm footprint, 0.65 mm pitch, 0.95 mm max height; thermally optimized for FR4 PCBs with single-sided 35 µm copper.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual PNP resistor-equipped transistor applications.

Compared with PUMD3 and PUMH11, the PUMB11 uniquely provides dual PNP topology with isolated emitters - essential for common-anode LED multiplexing and negative-rail logic interfacing where channel independence and polarity consistency are mandatory.

Availability

PUMB11 is available at Aetrix Electronics and suitable for LED segment drivers, microcontroller GPIO expansion, logic-level signal inversion, and low-power sensor interface buffering requiring stable component supply and consistent SOT363-3 packaging.

Supply support for PUMB11 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, discrete, and MOSFET devices for automotive, industrial, and consumer markets.

The PUMB11 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered to simplify digital interface design by integrating biasing networks into miniature SMT packages for space- and cost-sensitive applications.

FAQ

What is the maximum allowable continuous current per channel?

The PUMB11 supports −100 mA continuous output current per transistor under T_amb ≤ 25 °C with proper PCB thermal relief. Derating applies above 25 °C per the 417 K/W junction-to-ambient thermal resistance; at 70 °C ambient, max current drops to approximately −65 mA per channel to maintain T_j ≤ 150 °C.

Can Pins 1 and 4 be tied together externally?

Yes - GND1 (Pin 1) and GND2 (Pin 4) may be connected externally to share a common emitter reference, but doing so eliminates channel isolation and may increase crosstalk in high-speed switching. The datasheet specifies independent operation; shared-emitter use requires verification of V_EB limits (−10 V max) and thermal coupling effects.

Is the PUMB11 qualified for automotive applications?

No - the PUMB11 is not automotive-qualified. Nexperia explicitly states in its legal disclaimers that unless otherwise specified, products like PUMB11 are not tested or warranted for automotive use. It lacks AEC-Q101 qualification and is intended for industrial, consumer, and computing applications only.

How does the R2/R1 ratio affect switching behavior?

The R2/R1 = 1.0 ±0.2 ratio ensures predictable base current mirroring during turn-on and controlled discharge during turn-off. This maintains consistent V_CE(sat) and prevents latch-up in cascaded logic stages; deviation beyond ±20% risks incomplete saturation or slow turn-off due to insufficient base recombination current.