Nexperia USA Inc. PUMB13,115

Overview

PUMB13 from Nexperia is a PNP/PNP resistor-equipped double transistor (RET) in SOT363-3 (SC-88) package, featuring built-in bias resistors R1 = 4.7 kΩ and R2 = 47 kΩ, −50 V V_CEO, −100 mA I_O, and 300 mW total power dissipation. It functions as a dual low-side switch for digital logic interfacing and peripheral control in space-constrained PCBs.

For engineers reviewing the PUMB13 datasheet, PUMB13 pinout, PUMB13 application, or PUMB13 equivalent, this page delivers verified electrical parameters, validated pin assignments, confirmed thermal derating behavior, and real-world use cases in IO buffering and discrete logic replacement-enabling rapid schematic integration without external bias network design.

Technical Context

The PUMB13 integrates two matched PNP transistors with on-chip base bias networks (R1/R2 ratio = 10), eliminating discrete resistors while preserving DC current gain (h_FE ≥ 100 at −10 mA IC) and fast switching (f_T = 180 MHz). Each transistor operates independently with open-base V_CEO = −50 V and V_CE(sat) ≤ −100 mV at −5 mA/−0.25 mA drive.

Thermal performance is defined for FR4 PCB mounting: per-device R_th(j-a) = 417 K/W and power derating begins linearly above 25 °C ambient, reaching zero dissipation at 175 °C. Junction temperature is limited to 150 °C, and storage temperature spans −65 °C to +150 °C.

Key Specifications

Pinout & Package

SOT363-3 (SC-88 / TSSOP6) surface-mount plastic package: 2.2 mm × 1.35 mm footprint, 0.65 mm pitch, 0.95 mm max height, with exposed pad not present. Designed for reflow soldering using standard IPC-7351B footprint (2.35 mm × 0.4 mm solder lands).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual PNP resistor-equipped transistor applications.

Compared with PUMD13 and PUMH13, the PUMB13 uniquely supports dual active-low switching without polarity inversion or mixed-technology constraints, making it optimal for consolidated sink-only loads like LED arrays, reset lines, and interrupt request lines in embedded controllers.

Availability

PUMB13 is available at Aetrix Electronics and suitable for LED driver interfaces, microcontroller GPIO expansion, legacy TTL/CMOS input control, and power sequencing monitors requiring stable component supply across automotive infotainment, industrial HMI, and consumer IoT production programs.

Supply support for PUMB13 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability essential semiconductors-including logic, discretes, MOSFETs, and ESD protection-designed for mass-market electronics.

The PUMB13 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to replace discrete transistor-resistor combinations in digital interface and peripheral driver applications-reducing design complexity and manufacturing cost.

FAQ

What is the maximum allowable continuous current per transistor in the PUMB13?

The PUMB13 supports −100 mA continuous output current per transistor under T_amb ≤ 25 °C with proper PCB thermal relief. Derating applies above 25 °C ambient per Figure 1: at 75 °C ambient, maximum per-transistor current drops to approximately −60 mA to maintain junction temperature ≤ 150 °C on standard FR4.

Can the PUMB13 be used with 1.8 V logic inputs?

Yes-the PUMB13's V_I(on) is −0.9 V typical at −5 mA collector current, meaning a 1.8 V logic high applied to I1 or I2 produces sufficient base-emitter forward bias (V_BE ≈ −0.7 V) to saturate the transistor. Verified operation down to 1.65 V logic high is confirmed in datasheet Figure 5 across −40 °C to +100 °C.

Is there a thermal pad or exposed metal on the SOT363-3 package?

No-the SOT363-3 package used for PUMB13 has no thermal pad or exposed copper die attach paddle. Thermal dissipation relies entirely on leadframe conduction through the six gull-wing leads into the PCB copper, with R_th(j-a) = 417 K/W specified for single-sided FR4 mounting per datasheet Table 6.

How does the R2/R1 ratio affect switching behavior?

The R2/R1 = 10 ratio sets the internal base shunt-to-drive resistor relationship, ensuring adequate base current for saturation while preventing excessive base drive that could cause slow turn-off or increased power loss. This fixed ratio maintains consistent h_FE-independent switching thresholds across process and temperature variations, unlike discrete resistor designs.