Nexperia USA Inc. PUMB16,115

Overview

PUMB16 from Nexperia is a dual PNP resistor-equipped transistor (RET) in SOT363 (SC-88) package, featuring integrated bias resistors R1 = 22 kΩ and R2 = 47 kΩ, V_CEO = −50 V, I_O = −100 mA per transistor, and h_FE ≥ 80 at I_C = −5 mA. It serves as a compact, pre-biased switching pair for digital logic interfacing and low-current peripheral control in space-constrained PCBs.

For engineers reviewing the PUMB16 datasheet, PUMB16 pinout, PUMB16 application, or PUMB16 equivalent, key selection criteria include verified dual-PNP topology with matched R1/R2 ratio (1.7–2.6), guaranteed −50 V V_CEO, thermal resistance of 416 K/W (per device), and SC-88 footprint compatibility with high-density routing and reflow-only assembly.

Technical Context

This device integrates two independent PNP transistors with on-chip base-emitter bias networks-R1 connects base to input, R2 connects base to emitter-enabling direct TTL/CMOS-level drive without external resistors. Each transistor operates with open-base V_CEO = −50 V and supports I_C up to −100 mA under continuous DC conditions.

The R2/R1 ratio of 2.1 (typ.) ensures stable saturation behavior across temperature (−40 °C to +150 °C), while V_I(on) = −1.1 V (typ.) and V_I(off) = −0.8 V (typ.) define clean digital switching thresholds compatible with 3.3 V and 5 V logic families.

Key Specifications

Pinout & Package

SOT363 (SC-88) 6-pin plastic surface-mount package, 1.3 mm × 2.1 mm footprint, 0.65 mm pitch, designed for reflow soldering only. Pin 1 marked by notch or bevel.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-PNP resistor-equipped transistor applications.

Compared with NSVD2T2220MXV6T1G and EMZ6T2R, PUMB16 uniquely delivers matched dual-PNP topology with R2/R1 = 2.1, enabling superior noise-immune saturation in low-voltage logic interfaces while maintaining minimal 1.3 mm × 2.1 mm SC-88 footprint.

Availability

PUMB16 is available at Aetrix Electronics and suitable for industrial sensor interfaces, USB peripheral power control, LED driver circuits, and microcontroller GPIO expansion requiring stable component supply and long-term production continuity.

Supply support for PUMB16 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global leader in discrete, logic, and PowerMOS semiconductors, spun off from NXP in 2017 and focused on high-volume, high-reliability components for automotive, industrial, and computing markets.

PUMB16 belongs to Nexperia's resistor-equipped transistor (RET) product line, engineered specifically to replace discrete BJT-resistor combinations in digital switching applications while improving assembly yield and board density.

FAQ

What is the maximum operating temperature for PUMB16?

The junction temperature (T_j) must not exceed +150 °C, and the ambient temperature range is −65 °C to +150 °C. At T_amb = +85 °C, the device sustains −100 mA per transistor with P_tot derated to ~180 mW based on R_th(j-a) = 416 K/W. Thermal design must ensure PCB copper area meets FR4 single-sided tin-plated standard footprint requirements.

Can PUMB16 be used with 1.8 V logic inputs?

No-PUMB16 requires minimum V_I(on) ≈ −1.1 V (typ.) to reliably saturate; 1.8 V logic outputs cannot provide sufficient negative bias swing. It is validated for 3.3 V and 5 V CMOS/TTL systems where V_OH ≥ 2.4 V ensures adequate overdrive. For 1.8 V interfaces, a level shifter or alternative RET with lower V_I(on) is required.

Is PUMB16 pin-compatible with PEMB16?

No-PUMB16 uses SOT363 (SC-88) with 6-pin layout matching Table 3 pinning, while PEMB16 uses SOT666 with identical pin numbering but different physical dimensions and thermal pad structure. Footprint, solder stencil, and reflow profile differ; PCB redesign is required for substitution.

What is the meaning of marking code 'B*7' on PUMB16?

The marking 'B*7' identifies the PUMB16 device per Table 5; the asterisk denotes manufacturing location-'p' for Hong Kong, 't' for Malaysia, or 'W' for China-and '7' is the date code suffix. This marking is laser-etched on the top surface and aligns with Nexperia's traceability standards for lot tracking and quality assurance.