Nexperia USA Inc. PUMB17,115

Overview

PUMB17 from Nexperia is a dual PNP resistor-equipped transistor in SOT363 (SC-88) package, featuring integrated bias resistors R1 = 47 kΩ and R2 = 22 kΩ, V_CEO = −50 V, I_O = −100 mA, and P_tot = 300 mW per device. It functions as a compact, pre-biased digital switch for low-current peripheral driving and IC input control in space-constrained PCBs.

For engineers reviewing the PUMB17 datasheet, PUMB17 pinout, PUMB17 application, or PUMB17 equivalent, this device is selected for its reduced component count in logic-level interfacing, simplified base-drive design, and thermal performance on FR4 boards with reflow-only assembly.

Technical Context

The PUMB17 integrates two matched PNP transistors with on-chip base-emitter bias networks (R1/R2 ratio = 0.47 typ), eliminating external resistors for digital switching. Each transistor operates with open-base V_CEO = −50 V and supports DC output current up to −100 mA.

Its dual-transistor topology enables complementary signal inversion or parallel load driving within one SC-88 footprint. Thermal resistance is 416 K/W (junction-to-ambient, per device), validated under standard FR4 single-sided copper conditions with reflow soldering only.

Key Specifications

Pinout & Package

SOT363 (SC-88) is a 6-pin plastic surface-mounted package measuring 2.2 mm × 1.8 mm × 1.15 mm, optimized for high-density routing and automated placement. Pin 1 is marked by a notch or dot; device orientation follows JEITA standard SC-88 outline.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual PNP pre-biased transistor applications.

Compared with NSVD2101PT3G and EMB17T2R, PUMB17 offers optimal balance of low VI(on) (−2.7 V typ), tight R2/R1 ratio tolerance (±0.1), and documented reflow-only process compliance-making it preferred for high-volume consumer and industrial control designs requiring predictable turn-on behavior.

Availability

PUMB17 is available at Aetrix Electronics and suitable for LED display drivers, microcontroller I/O expansion, industrial sensor conditioning, and power rail enable control requiring stable component supply across production lifecycles.

Supply support for PUMB17 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global leader in discrete, logic, and PowerMOS semiconductors, formed in 2017 from the former NXP Standard Products business, with focus on automotive, industrial, computing, and consumer markets.

PUMB17 belongs to Nexperia's resistor-equipped transistor (RET) product line, engineered to replace general-purpose transistors in digital logic interfacing by integrating precision bias networks for zero-component-count switching.

FAQ

What is the maximum allowable junction temperature for continuous operation?

The absolute maximum junction temperature (T_j) is 150 °C, as defined in the limiting values table. Operation at this temperature requires derating total power dissipation based on ambient conditions and PCB thermal design. At T_amb = 85 °C, maximum usable P_tot drops to approximately 120 mW per device using the specified R_th(j-a) = 416 K/W.

Can PUMB17 be used in analog amplification applications?

No-PUMB17 is designed exclusively for digital switching. Its fixed R1/R2 bias network prevents stable DC operating point adjustment required for linear amplification. The h_FE specification applies only under saturated switching conditions (V_CE = −5 V), and no small-signal parameters (e.g., f_T, C_ob) are characterized for analog use.

Is PUMB17 compatible with lead-free reflow profiles per J-STD-020?

Yes-Nexperia qualifies PUMB17 for lead-free reflow only, with peak temperature up to 260 °C. The datasheet explicitly prohibits wave and hand soldering. Thermal resistance data (R_th(j-a)) is measured under reflow conditions on FR4 with standard footprint, confirming process alignment.

How does the R2/R1 ratio affect switching behavior?

The R2/R1 ratio (0.47 typ) sets the internal feedback fraction that stabilizes the base-emitter voltage during turn-on. A lower ratio increases base current for faster saturation but raises standby current; PUMB17's 0.47 value balances speed (<100 ns t_on), leakage (<1 µA ICEO), and noise immunity across −40 °C to +125 °C.