Nexperia USA Inc. PUMB1/DG/B3,115

Overview

PUMB1/DG/B3,115 from Nexperia is a dual PNP resistor-equipped transistor (RET) in SOT363 (SC-88) surface-mount package, configured as two independent PNP transistors with integrated 22 kΩ input bias resistors (R1) and matched R2/R1 ratio of 1.0. It delivers −100 mA output current per transistor, supports −50 V collector-emitter voltage, and is AEC-Q101 qualified for automotive signal conditioning and digital logic interface applications.

For engineers reviewing the PUMB1/DG/B3,115 datasheet, PUMB1/DG/B3,115 pinout, PUMB1/DG/B3,115 application, or PUMB1/DG/B3,115 equivalent, this device serves as a space-optimized, bias-resistor-integrated replacement for discrete PNP pairs in level-shifting, I/O buffering, and low-power peripheral driver circuits where board area and assembly cost are critical.

Technical Context

This dual PNP RET integrates two matched PNP transistors with monolithically embedded 22 kΩ base-input resistors (R1) and feedback resistors (R2), enabling direct TTL/CMOS-compatible logic-level drive without external bias components. Each transistor operates with V_CEO = −50 V and I_O = −100 mA under DC conditions.

The device features symmetric pinning (GND–IN–OUT for TR1; GND–IN–OUT for TR2), thermal resistance R_th(j-a) = 417 K/W per device on FR4 PCB, and guaranteed operation from −65 °C to +150 °C ambient, supporting robust performance in automotive engine control modules and industrial sensor interfaces.

Key Specifications

Pinout & Package

SOT363 (SC-88) 6-pin ultra-small flat-lead plastic package, 2.0 mm × 1.25 mm body size, 0.65 mm pitch, lead-free and RoHS compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual PNP resistor-equipped transistor applications.

Compared with NSVD2P0233MUTBG and EMX23T2R, PUMB1/DG/B3,115 uniquely provides matched dual-PNP topology with identical 22 kΩ bias networks and −100 mA per channel capability in a single SC-88 package-making it optimal for space-constrained, high-reliability dual-sink applications where channel matching and AEC-Q101 compliance are mandatory.

Availability

PUMB1/DG/B3,115 is available at Aetrix Electronics and suitable for automotive body control modules, industrial programmable logic controller (PLC) input stages, and portable medical device I/O expansion requiring stable component supply, long-term lifecycle support, and AEC-Q101 traceability.

Supply support for PUMB1/DG/B3,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global leader in discrete, logic, and PowerMOS semiconductors, spun off from NXP in 2017 and focused on high-volume, high-reliability components for automotive, industrial, and computing markets.

PUMB1 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to replace discrete transistor-resistor combinations in digital interface and peripheral driver applications where miniaturization and assembly efficiency are critical.

FAQ

What is the maximum junction temperature and how does it affect continuous operation?

The absolute maximum junction temperature is 150 °C. At ambient temperatures up to 85 °C, the device sustains full −100 mA per channel output with derated power dissipation (300 mW → ~180 mW at 85 °C). Thermal resistance of 417 K/W (per device) means 100 mW power dissipation raises junction temperature by 41.7 °C above ambient-enabling reliable operation in sealed automotive enclosures without heatsinking.

Can PUMB1/DG/B3,115 be used in linear amplifier mode?

No. This device is optimized for digital switching operation only. Its integrated bias resistors fix base current, and h_FE is specified only at I_C = −5 mA with V_CE = −5 V. The datasheet provides no small-signal parameters (e.g., g_m, f_T linearity, or distortion data), and V_CE(sat) is characterized only for saturated switching-not linear region biasing.

How does the R2/R1 ratio impact switching behavior?

The R2/R1 ratio of 1.0 ±20% ensures consistent feedback from collector to base, stabilizing saturation depth and reducing sensitivity to transistor h_FE variation. At I_C = −10 mA, this ratio maintains V_CE(sat) ≤ −150 mV across temperature (−40 °C to +125 °C), preventing unintended partial conduction in noise-prone environments like motor drive feedback loops.

Is wave soldering supported for the SOT363 package?

No. The datasheet explicitly states "Reflow soldering is the only recommended soldering method." Wave soldering is not characterized for PUMB1/DG/B3,115 and risks thermal damage due to its ultra-small geometry and internal resistor trimming. Figure 14 shows a wave footprint for legacy reference only; actual production must use reflow per J-STD-020 profile with peak temperature ≤260 °C.