Nexperia USA Inc. PUMB2/DG/B3,115

Overview

PUMB2/DG/B3,115 from NXP Semiconductors is a dual PNP resistor-equipped transistor (RET) in SOT363 (SC-88) surface-mount package, configured as two independent PNP transistors with integrated 47 kΩ input bias resistors (R1) and matched R2/R1 ratio of 1.0. It delivers −100 mA output current per transistor, supports −50 V collector-emitter voltage, and is AEC-Q101 qualified for automotive signal-level switching applications such as LED driver control and logic-level translation.

For engineers reviewing the PUMB2/DG/B3,115 datasheet, PUMB2/DG/B3,115 pinout, PUMB2/DG/B3,115 application, or PUMB2/DG/B3,115 equivalent, this device serves as a space- and BOM-optimized replacement for discrete PNP pairs in low-power digital interface circuits - particularly where input threshold control, thermal stability up to 150 °C junction temperature, and reflow-only soldering compatibility are required.

Technical Context

This dual RET integrates two matched PNP bipolar transistors with monolithically embedded base bias networks (R1 = 47 kΩ, R2 = 47 kΩ), eliminating external resistors and reducing PCB footprint. Each transistor operates with V_CEO = −50 V and I_O = −100 mA under DC conditions, with typical h_FE ≥ 80 at I_C = −5 mA and V_CE = −5 V.

The device uses a common-emitter configuration per channel, with dedicated GND (emitter), input (base), and output (collector) terminals assigned to each transistor. Its SC-88 package enables high-density placement while maintaining thermal resistance of 417 K/W (per device) on FR4 PCBs, supporting stable operation across −65 °C to +150 °C ambient range.

Key Specifications

Pinout & Package

SOT363 (SC-88) 6-pin ultra-small flat lead package, 2.2 mm × 1.35 mm × 0.95 mm body size, with gull-wing leads and pin 1 index marker. Designed for reflow-only assembly per JEDEC J-STD-020.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual PNP resistor-equipped transistor applications.

Compared with NSVD2101PT3G and EMX12T2R, PUMB2/DG/B3,115 uniquely delivers two matched PNP channels in one SC-88 package with identical biasing, enabling compact, thermally balanced dual-signal control without layout compromises or performance trade-offs.

Availability

PUMB2/DG/B3,115 is available at Aetrix Electronics and suitable for automotive lighting control, industrial PLC input conditioning, and consumer appliance keypad scanning requiring stable component supply, long-term lifecycle assurance, and AEC-Q101-compliant sourcing.

Supply support for PUMB2/DG/B3,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT applications.

PUMB2 belongs to NXP's Resistor-Equipped Transistor (RET) product line, designed specifically to reduce component count and improve reliability in digital interface and low-power switching circuits across automotive and industrial markets.

FAQ

What is the maximum allowable continuous current per transistor in PUMB2/DG/B3,115?

The absolute maximum continuous output current per transistor is −100 mA, as specified in Table 5 (Limiting Values) under "IO output current". This rating applies at Tamb ≤ 25 °C with standard FR4 PCB mounting. Derating is required above 25 °C ambient per the power derating curve in Figure 1, where total device power dissipation drops to 200 mW at 85 °C ambient.

Does PUMB2/DG/B3,115 support wave soldering?

No - reflow soldering is the only recommended method, as explicitly stated in Section 11 ("Soldering") and Table 9. Wave soldering is not qualified for this device; Figure 14 shows a wave footprint for PUMB2 but notes it is for reference only and does not imply qualification. Using wave soldering risks thermal damage due to the SC-88 package's sensitivity and may void AEC-Q101 compliance.

How are the two transistors inside PUMB2/DG/B3,115 electrically isolated?

The two PNP transistors share no internal electrical connection - their emitters (Pins 1 and 4), bases (Pins 2 and 5), and collectors (Pins 6 and 3) are fully independent. The datasheet confirms this in Table 3 ("Pinning") and Figure 3's graphic symbol, which shows two separate transistor symbols with distinct terminals. No shared substrate or backside connection is defined.

Can PUMB2/DG/B3,115 replace discrete BC856BS transistors in existing designs?

Yes - with layout adaptation. Each PUMB2 channel matches BC856BS (PNP, hFE ≥ 110, VCEO = −65 V) in polarity and general function, but adds integrated 47 kΩ bias resistors. To substitute, remove external base resistors and route MCU GPIO directly to Pins 2/5. Verify VI(on)/VI(off) thresholds (−1.6 V / −1.2 V) align with controller logic levels, and confirm thermal design accommodates 417 K/W θ_j-a.