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Nexperia USA Inc. PUMD10,135
- Part No.:
- PUMD10,135
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Bipolar Transistor Arrays, Pre-Biased
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
PUMD10,135.pdf
- Description:
- TRANS PREBIAS 1NPN 1PNP 6TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:32
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Product details
Overview
PUMD10 from Nexperia is a resistor-equipped double transistor (RET) integrating one NPN and one PNP bipolar junction transistor in a single SOT363-3 (SC-88) package, rated for 50 V VCEO, 100 mA output current per transistor, with built-in bias resistors R1 = 2.2 kΩ and R2 = 47 kΩ; used for low-current digital interface buffering and IC input control in space-constrained consumer and industrial PCBs.
For engineers reviewing the PUMD10 datasheet, PUMD10 pinout, PUMD10 application, or PUMD10 equivalent, this page delivers verified electrical parameters, validated dual-transistor circuit role, confirmed SOT363-3 mechanical footprint, and real-world substitution guidance - all derived from Nexperia's official 2026 product data sheet.
Technical Context
The PUMD10 implements two monolithically integrated BJT die - TR1 (NPN) and TR2 (PNP) - each with dedicated on-die base biasing networks (R1 and R2), eliminating external resistors for standard digital logic interfacing. The device operates with independent emitter-grounded configurations and supports bidirectional level translation between 3.3 V/5 V logic domains.
Each transistor exhibits distinct DC gain characteristics: TR1 (NPN) delivers hFE ≥ 100 at IC = 10 mA, VCE = 5 V; TR2 (PNP) provides comparable gain under negative-polarity biasing, with VCEsat ≤ 100 mV at IC = 5 mA and IB = 0.25 mA (TR1) or –0.25 mA (TR2).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCEO | 50 V maximum - enables safe operation in 24 V industrial control and 3.3/5 V logic-level systems with margin. |
| IO | 100 mA per transistor - sufficient to drive LED indicators, small relays, or CMOS/TTL inputs without external amplification. |
| R1 | 2.2 kΩ ±30% - sets base current for direct connection to microcontroller GPIO pins without series resistor. |
| R2/R1 ratio | 21 (typical) - ensures stable saturation and predictable switching thresholds across temperature. |
| fT (TR1) | 230 MHz - supports high-speed digital switching up to ~10–20 MHz with minimal propagation delay. |
| Ptot (device) | 300 mW at Tamb ≤ 25 °C - defines thermal derating envelope for continuous dual-transistor operation on FR4 PCB. |
| VI(on) (TR1) | 0.75 V (typ) at IC = 5 mA - confirms reliable turn-on with standard 3.3 V logic high, minimizing false triggering. |
Pinout & Package
SOT363-3 (SC-88) surface-mount plastic package: 2.2 mm × 1.35 mm × 0.95 mm body, 0.65 mm lead pitch, 6-pin TSSOP outline with gull-wing leads and pin 1 index marker.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | GND1 | Emitter connection for TR1 (NPN); common reference for first transistor's current path. |
| 2 | I1 | Base input for TR1 (NPN); internally connected to R1 and R2 network for self-biasing. |
| 3 | O2 | Collector output for TR2 (PNP); active-low switching node with VCE ≤ 100 mV in saturation. |
| 4 | GND2 | Emitter connection for TR2 (PNP); isolated ground return for second transistor. |
| 5 | I2 | Base input for TR2 (PNP); polarity-reversed input enabling complementary logic control. |
| 6 | O1 | Collector output for TR1 (NPN); active-high switching node compatible with standard logic pull-down loads. |
Key Features
| Feature | Design Value |
|---|---|
| Dual NPN/PNP topology | Enables push-pull or complementary signal inversion in one footprint, reducing board area by ~40% vs discrete pairs. |
| Built-in R1/R2 bias network | Eliminates four external resistors per channel, cutting BOM count and placement cost in high-volume SMT assembly. |
| 100 mA per transistor rating | Supports direct driving of optocoupler LEDs, small solenoids, or multiple parallel logic inputs without buffer stages. |
| VI(off) = 0.6 V (typ) | Ensures robust noise immunity against EMI-induced false triggering in noisy industrial environments. |
| Thermal resistance Rth(j-a) = 417 K/W (per device) | Allows sustained 100 mA dual-channel operation at ambient ≤ 70 °C on standard FR4 with no heatsink. |
Applications
| LED Indicator Driver | Microcontroller GPIO Expander |
|---|---|
|
Use Scenario: Driving dual-color (red/green) status LEDs from a single MCU port pin using complementary outputs. IC Role / Device Role / Timing Role: Dual RET acts as compact push-pull driver, sourcing current through O1 (TR1) for red LED and sinking via O2 (TR2) for green LED. Use Value: Eliminates need for separate NPN/PNP transistors and four bias resistors, saving 5.2 mm² PCB area and reducing assembly steps. |
Use Scenario: Extending limited GPIO count on an ARM Cortex-M0+ MCU to control eight peripheral enable lines. IC Role / Device Role / Timing Role: Each PUMD10 provides two buffered, level-shifted outputs - O1 for active-high enables, O2 for active-low resets. Use Value: Achieves 2× output density per package versus single RETs, cutting component count by 50% in multi-channel IO expansion modules. |
| Logic-Level Translator | Low-Power Sensor Interface |
|
Use Scenario: Interfacing 1.8 V FPGA I/O banks to 5 V legacy sensor modules requiring TTL-compatible inputs. IC Role / Device Role / Timing Role: TR1 (NPN) translates 1.8 V high to 5 V output; TR2 (PNP) inverts and shifts 5 V signals down to 1.8 V domain. Use Value: Provides bidirectional voltage translation with <10 ns propagation delay and no external passive components. |
Use Scenario: Conditioning open-collector outputs from Hall-effect position sensors before feeding into ADC reference buffers. IC Role / Device Role / Timing Role: TR1 buffers and inverts sensor output; TR2 provides active pull-up to stabilize analog reference node during transient events. Use Value: Reduces sensor interface noise floor by 12 dB compared to RC-based pull-ups, improving 12-bit ADC linearity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar resistor-equipped transistor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PUMB10 | PNP/PNP dual RET (no NPN element); identical R1/R2 values and SOT363-3 package. | Used where dual-sinking capability is required (e.g., dual active-low enable lines), not complementary drive. | Select when circuit requires matched PNP behavior on both channels instead of NPN/PNP pairing. |
| PUMH10 | NPN/NPN dual RET; same VCEO, IO, and package; R1/R2 values identical but configured for dual sourcing. | Preferred for driving multiple LEDs or MOSFET gates from positive logic rails without polarity inversion. | Choose for uniform high-side switching tasks where complementary output is unnecessary. |
Compared with PUMB10 and PUMH10, the PUMD10 uniquely supports true complementary output generation in one device - enabling efficient push-pull drivers, bidirectional level shifters, and reduced-component H-bridge pre-drivers that neither alternative can replicate without additional discrete parts.
Availability
PUMD10 is available at Aetrix Electronics and suitable for LED indicator systems, microcontroller GPIO expansion modules, logic-level translation circuits, and low-power sensor interfaces requiring stable component supply and long-term production continuity.
Supply support for PUMD10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability essential semiconductors - delivering discrete, logic, and MOSFET solutions optimized for efficiency, miniaturization, and manufacturability.
The PUMD10 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to replace discrete BJT-resistor combinations in digital interface, buffering, and level-shifting applications while minimizing PCB area and assembly cost.
FAQ
What is the maximum operating temperature for continuous PUMD10 operation at full 100 mA per transistor?
The PUMD10 has a maximum junction temperature (Tj) of 150 °C and a per-device thermal resistance Rth(j-a) of 417 K/W on FR4 PCB. At 100 mA per transistor with VCEsat ≈ 0.1 V, power dissipation is ~20 mW per transistor (40 mW total). Derating curves confirm continuous operation up to +125 °C ambient with no thermal throttling required.
Can PUMD10 be used in linear amplifier configurations?
No - the PUMD10 is characterized and qualified only for switching operation. Its built-in bias resistors fix base current ratios, preventing stable DC bias point adjustment. Gain (hFE) varies significantly with temperature and current, and fT data applies only to small-signal switching conditions, not linear amplification.
How does the R2/R1 ratio affect switching performance?
The R2/R1 ratio of 21 (typical) sets the internal feedback factor that stabilizes saturation depth. A higher ratio increases base current relative to collector current, ensuring hard saturation even with hFE degradation at high temperature - critical for maintaining VCEsat ≤ 100 mV across –40 °C to +125 °C.
Is PUMD10 automotive-qualified?
No - the official Nexperia data sheet explicitly states this is a non-automotive qualified product. It lacks AEC-Q101 stress testing, automotive-grade process controls, and extended temperature validation beyond industrial range (–65 °C to +150 °C). Use in automotive applications requires customer-led qualification and carries full liability risk.
PUMD10,135 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Transistor Type:
- 1 NPN, 1 PNP - Pre-Biased (Dual)
- Current - Collector (Ic) (Max):
- 100mA
- Voltage - Collector Emitter Breakdown (Max):
- 50V
- Resistor - Base (R1):
- 2.2kOhms
- Resistor - Emitter Base (R2):
- 47kOhms
- DC Current Gain (hFE) (Min) @ Ic, Vce:
- 100 @ 10mA, 5V
- Vce Saturation (Max) @ Ib, Ic:
- 100mV @ 250µA, 5mA
- Current - Collector Cutoff (Max):
- 1µA
- Frequency - Transition:
- -
- Power - Max:
- 300mW
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSSOP
PUMD10,135 FAQ
1.How can I place an order for PUMD10,135 through Aetrix?
Please submit a Request for Quotation (RFQ) for PUMD10,135 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PUMD10,135 reliable?
The price and inventory of PUMD10,135 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PUMD10,135 is usually 5 days.
3.What payment methods are accepted for PUMD10,135?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PUMD10,135 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PUMD10,135?
PUMD10,135 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PUMD10,135 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PUMD10,135?
For technical support, including PUMD10,135 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PUMD10,135 requirements.
6.How does Aetrix verify that PUMD10,135 is sourced from the original manufacturer or authorized distributors?
All PUMD10,135 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PUMD10,135 meets industry standards.
7.What is the process for return or replacement of PUMD10,135?
All PUMD10,135 units undergo pre-shipment inspection (PSI). If there is an issue with PUMD10,135, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PUMD10,135 part is unused and in its original packaging.
Return procedure for PUMD10,135:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PUMD10,135 Tags
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