Nexperia USA Inc. PUMD10-QH

Overview

PUMD10-QH from Nexperia is a resistor-equipped double transistor (RET) integrating one NPN and one PNP silicon bipolar transistor with built-in bias resistors (R1 = 2.2 kΩ, R2 = 47 kΩ) in a single SOT363-3 (TSSOP6) package. It delivers 100 mA output current per transistor, supports ±50 V collector-emitter voltage, and is AEC-Q101 qualified for automotive signal-level switching and digital interface control.

For engineers reviewing the PUMD10-QH datasheet, PUMD10-QH pinout, PUMD10-QH application, or PUMD10-QH equivalent, this device serves as a space- and BOM-optimized replacement for discrete NPN+PNP pairs in low-current peripheral drivers, IC input control, and automotive body electronics where simplified biasing and reduced assembly cost are critical.

Technical Context

The PUMD10-QH implements two monolithically integrated bipolar transistors - TR1 (NPN) and TR2 (PNP) - each with dedicated on-chip base bias networks (R1 and R2), eliminating external resistors. Its dual-polarity configuration enables complementary switching in level translation, push-pull drivers, and logic inverters without cross-coupling.

Each transistor operates independently with verified DC current gain (hFE ≥ 100 at IC = 10 mA, VCE = 5 V), saturation voltage ≤ 100 mV (IC = 5 mA, IB = 0.25 mA), and transition frequencies of 230 MHz (NPN) and 180 MHz (PNP), confirming suitability for medium-speed digital switching up to ~50 MHz.

Key Specifications

Pinout & Package

Package: SOT363-3 (TSSOP6), 1.3 mm × 2.2 mm × 0.95 mm, 6-pin surface-mount plastic package with gull-wing leads and exposed thermal pad-compatible footprint.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar resistor-equipped transistor applications.

Compared with PUMB10-Q and PUMH10-Q, the PUMD10-QH uniquely supports true complementary output behavior (one sink + one source) within a single footprint, enabling compact push-pull drivers, bidirectional level shifters, and reduced interconnect in mixed-voltage systems.

Availability

PUMD10-QH is available at Aetrix Electronics and suitable for automotive body electronics, industrial PLC I/O modules, USB-C port controllers, and smart lighting systems requiring stable component supply, AEC-Q101 compliance, and high-volume manufacturability.

Supply support for PUMD10-QH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-performance, energy-efficient logic, discrete, and MOSFET solutions, serving automotive, industrial, and consumer markets with AEC-Q101-qualified components.

The PUMD10-QH belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to replace discrete transistor-resistor combinations in space-constrained, high-reliability digital interface applications.

FAQ

What is the maximum operating junction temperature for PUMD10-QH?

The absolute maximum junction temperature (T_j) is 150 °C, validated per IEC 60134 limiting values. At ambient temperatures up to 105 °C, the device maintains full 100 mA output capability when mounted on FR4 PCB with standard single-sided copper footprint, as confirmed by thermal resistance data (R_th(j-a) = 417 K/W per device).

Can PUMD10-QH be used with 1.8 V logic inputs?

No - the minimum guaranteed VI(on) is 0.75 V (typical) for the NPN section and −0.75 V for the PNP section, but reliable turn-on requires ≥1.1 V (NPN) or ≤−1.1 V (PNP) per datasheet characteristics. Driving from 1.8 V logic is acceptable; sub-2.0 V CMOS outputs may not achieve full saturation due to insufficient base overdrive.

Is there crosstalk between the NPN and PNP sections?

No measurable electrical crosstalk exists - the transistors share only substrate isolation, with independent emitter terminals (GND1 and GND2), separate bias networks, and no shared collector or base paths. Layout-dependent capacitive coupling is limited to <3 pF (TR2 C_c) and does not affect functional switching integrity at ≤10 MHz.

How does the R2/R1 ratio impact switching performance?

The R2/R1 ratio (21 ±24%) determines the internal feedback factor that stabilizes the base bias point against temperature drift and h_FE variation. A higher ratio increases noise immunity and reduces sensitivity to input leakage, while maintaining fast turn-off by ensuring adequate base discharge through R2 during transistor cutoff.