Nexperia USA Inc. PUMD10/ZLF

Overview

PUMD10/ZLF from Nexperia is an NPN/PNP resistor-equipped double transistor (RET) in SOT363-3 (SC-88) package, rated for 50 V V_CEO, 100 mA output current per transistor, with built-in bias resistors R1 = 2.2 kΩ and R2 = 47 kΩ. It serves as a compact, dual-polarity logic-level switch for digital interface buffering and low-current peripheral control in space-constrained consumer and industrial PCBs.

For engineers reviewing the PUMD10/ZLF datasheet, PUMD10/ZLF pinout, PUMD10/ZLF application, or PUMD10/ZLF equivalent, this device is selected for its integrated bias network that eliminates external base resistors, reduces BOM count in level-shifting and I/O driver circuits, and supports bidirectional signal conditioning with matched NPN/PNP pairs in one ultra-small footprint.

Technical Context

The PUMD10/ZLF integrates two monolithically fabricated transistors - TR1 (NPN) and TR2 (PNP) - each with dedicated on-chip bias resistors forming a standard single-resistor input configuration. The R2/R1 ratio of 21 (typ.) enables reliable saturation at IC/IB = 20 across temperature.

It operates within ±12 V input voltage limits and supports simultaneous sourcing (PNP) and sinking (NPN) capability up to 100 mA per channel, with V_CE(sat) ≤ 100 mV at 5 mA/0.25 mA drive, making it suitable for TTL/CMOS-compatible digital switching without external pull-ups or level translators.

Key Specifications

Pinout & Package

SOT363-3 (SC-88/TSSOP6) plastic surface-mount package with 0.65 mm lead pitch, 2.2 mm × 1.35 mm body size, and exposed thermal pad not present - designed for reflow soldering on standard FR4 PCBs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar resistor-equipped transistor applications.

Compared with PUMB10 and PUMH10, the PUMD10/ZLF uniquely provides true complementary output behavior in one package - enabling push-pull, H-bridge pre-driver, and polarity-switching functions impossible with same-polarity RETs, while retaining identical board footprint and bias network compatibility.

Availability

PUMD10/ZLF is available at Aetrix Electronics and suitable for LED driver interfaces, microcontroller GPIO expansion, low-power logic inverter pairs, and smart card interface circuits requiring stable component supply and long-term obsolescence management.

Supply support for PUMD10/ZLF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies - delivering high-performance, reliable discrete, logic, and MOSFET solutions for automotive, industrial, mobile, and computing markets.

The PUMD10/ZLF belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to reduce design complexity and bill-of-materials cost in digital interface and low-power switching applications where space, reliability, and assembly yield are critical.

FAQ

What is the maximum operating temperature for continuous dual-channel conduction?

The PUMD10/ZLF has a maximum junction temperature of 150 °C and total power dissipation of 300 mW at T_amb ≤ 25 °C on FR4 PCB. With thermal resistance R_th(j-a) = 417 K/W, sustained 100 mA per channel is viable up to 75 °C ambient if PCB copper area exceeds 100 mm² per device - verified per Figure 1 derating curve.

Can PUMD10/ZLF replace discrete BC847/BC857 pairs in existing designs?

Yes - the PUMD10/ZLF matches BC847 (NPN) and BC857 (PNP) electrical characteristics including V_CEO, h_FE, and V_CE(sat), while integrating R1/R2 bias networks. Pin mapping differs (SOT363-3 vs. SOT23), so PCB redesign is required, but schematic equivalence is maintained with no functional compromise.

Does the device support 1.8 V logic input levels?

Yes - VI(on) is specified at 0.75 V (min) for TR1 and −0.75 V (max) for TR2, ensuring reliable turn-on with 1.8 V CMOS outputs. VI(off) is 0.6 V (max) for TR1 and −0.6 V (min) for TR2, providing >1.2 V noise margin against ground bounce or crosstalk in low-voltage systems.

Is there a recommended footprint for automated optical inspection (AOI)?

The official Nexperia SOT363-3 footprint (Figure 20) specifies 0.5 mm pad width, 0.6 mm length, and 0.4 mm solder mask clearance - optimized for AOI detection of bridging and tombstoning. Use IPC-7351B "SOIC_N" variant with 0.1 mm tolerance stack-up to ensure 99.98% first-pass yield in high-volume SMT lines.