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Nexperia USA Inc. PUMD12/DG/B3,115
- Part No.:
- PUMD12/DG/B3,115
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Bipolar Transistor Arrays, Pre-Biased
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
PUMD12/DG/B3,115.pdf
- Description:
- TRANS PREBIAS 1NPN 1PNP 6TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:2,356
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Product details
Overview
PUMD12/DG/B3,115 from Nexperia is an NPN/PNP dual resistor-equipped transistor (RET) in a 6-pin SOT363 (SC-88) surface-mount package, integrating matched 47 kΩ input bias resistors and rated for 100 mA per transistor. It functions as a compact logic-level interface device for digital signal translation and low-power peripheral driving in space-constrained automotive and industrial control modules.
For engineers reviewing the PUMD12/DG/B3,115 datasheet, PUMD12/DG/B3,115 pinout, PUMD12/DG/B3,115 application, or PUMD12/DG/B3,115 equivalent, key selection criteria include its AEC-Q101 qualification, dual-polarity configuration, built-in R1/R2 = 47 kΩ/47 kΩ bias network, 50 V VCEO rating, and thermal resistance of 417 K/W (per device) on FR4 PCB.
Technical Context
This dual RET integrates one NPN (TR1) and one PNP (TR2) transistor with monolithically embedded base bias resistors-R1 (input) and R2 (feedback)-enabling direct TTL/CMOS logic interfacing without external components. The R2/R1 ratio is tightly controlled at 0.8–1.2, ensuring consistent switching thresholds across temperature.
Each transistor supports independent operation with separate emitter (GND), base (input), and collector (output) terminals. TR1 (NPN) delivers 230 MHz fT and 80 minimum hFE at 5 V VCE/5 mA IC; TR2 (PNP) provides 180 MHz fT and comparable saturation performance with −150 mV VCEsat at −10 mA IC/−0.5 mA IB.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCEO | 50 V - Maximum safe collector-emitter voltage for both transistors under open-base conditions, enabling use in 24 V industrial I/O and automotive body-control circuits. |
| IO | 100 mA - Continuous output current capability per transistor, sufficient for driving LEDs, small relays, and logic inputs without external current amplification. |
| R1 | 47 kΩ (33–61 kΩ range) - Integrated input bias resistor eliminates need for discrete pull-up/pull-down, reducing BOM count and PCB area in level-shifting applications. |
| R2/R1 ratio | 1.0 ±0.2 - Ensures stable turn-on/off behavior across temperature and process variation, critical for reliable digital switching in noise-prone environments. |
| fT (TR1) | 230 MHz - High transition frequency supports fast edge rates in signal buffering and pulse-width modulation (PWM) gate drive for low-side switches. |
| VI(on) | 1.6–3.0 V - On-state input voltage range confirms compatibility with 3.3 V and 5 V CMOS/TTL logic families without level translation. |
| Ptot (per device) | 300 mW - Total power dissipation limit at Tamb ≤25 °C, defining thermal design margin for continuous operation on standard FR4 PCBs. |
Pinout & Package
Package: SOT363 (SC-88), ultra-small 6-pin surface-mount plastic package with 0.65 mm pitch, 2.2 mm × 1.35 mm footprint, and exposed pad-compatible layout per Figure 17.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | GND (emitter of TR1) | Common reference node for NPN transistor; must be tied to system ground for proper biasing and current return path. |
| 2 | Input (base of TR1) | Logic input for NPN transistor; internally connected to R1; accepts 0–40 V positive signals with VI(off) ≥1.2 V for guaranteed off-state. |
| 3 | Output (collector of TR2) | Active-low output node for PNP transistor; sinks current when TR2 is on; used for high-side switching or inverted logic outputs. |
| 4 | GND (emitter of TR2) | Common reference for PNP transistor; electrically isolated from Pin 1 but typically connected to same ground plane. |
| 5 | Input (base of TR2) | Logic input for PNP transistor; internally biased via R1/R2 network; responds to negative-going signals with VI(off) ≤0.8 V for guaranteed off-state. |
| 6 | Output (collector of TR1) | Active-high output node for NPN transistor; sources current when TR1 is on; used for low-side switching or non-inverted logic outputs. |
Key Features
| Feature | Design Value |
|---|---|
| Dual NPN/PNP topology | Enables complementary signal generation (e.g., push-pull outputs or differential logic interfaces) within a single 2.2 mm × 1.35 mm footprint. |
| AEC-Q101 qualified | Validated for automotive-grade reliability including temperature cycling, humidity testing, and ESD robustness, supporting under-hood and infotainment applications. |
| Built-in 47 kΩ bias resistors | Eliminates four external resistors per channel, reducing placement cost by ~30% and minimizing solder joint failure risk in high-vibration environments. |
| Low VCEsat (≤150 mV) | Minimizes conduction loss in 3.3 V/5 V logic-driven loads, improving efficiency in battery-powered sensors and portable industrial tools. |
| Thermal resistance (Rth(j-a)) | 417 K/W (per device) on FR4 PCB enables sustained 100 mA operation up to +85 °C ambient without heatsinking. |
Applications
| Automotive Door Module | Industrial PLC Input Stage |
|---|---|
|
Use Scenario: Level-shifting and isolation of door lock/unlock switch signals between 12 V vehicle bus and 3.3 V microcontroller GPIO. IC Role / Device Role / Timing Role: Dual RET acts as bidirectional signal conditioner-TR1 buffers high-side switch closure; TR2 handles ground-referenced sensor feedback. Use Value: Reduces component count by replacing two discrete transistors + four bias resistors, meeting AEC-Q101 requirements without redesign. |
Use Scenario: Converting 24 V DC field sensor outputs to clean 5 V logic levels for FPGA-based control logic in factory automation cabinets. IC Role / Device Role / Timing Role: TR1 drives optocoupler LED anodes; TR2 provides active-low enable for downstream analog front-end power gating. Use Value: Built-in resistor matching ensures consistent rise/fall times (<100 ns) across channels, eliminating timing skew in synchronized I/O sampling. |
| USB-C Power Delivery Interface | Wearable Health Sensor Hub |
|
Use Scenario: Managing CC line detection and VCONN power switching in USB-C receptacle circuits where space and thermal budget are constrained. IC Role / Device Role / Timing Role: TR1 controls VCONN enable path; TR2 monitors CC voltage polarity and asserts fault flag to PD controller. Use Value: 300 mW total dissipation allows continuous operation at 85 °C ambient, avoiding thermal throttling during extended cable negotiation sequences. |
Use Scenario: Driving multiplexed LED indicators and enabling/disabling analog sensor bias rails in compact wearable ECG/SpO₂ modules. IC Role / Device Role / Timing Role: TR1 activates green LED status indicator; TR2 gates 1.8 V LDO enable for low-noise ADC reference circuitry. Use Value: SC-88 package fits within 3 mm² board area, and 100 nA ICBO ensures <1 µA standby current-extending battery life beyond 7 days. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual RET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NSVD20011MUTBG | Single-channel NPN RET (SOT-23); no PNP complement; R1 = 100 kΩ, R2 = 100 kΩ. | Requires two devices for NPN+PNP functionality; lacks integrated complementary pair. | Select when only unidirectional logic buffering is needed and board space permits dual placement. |
| EMX11T2R | PNP+NPN RET in SOT-563; R1 = 22 kΩ, R2 = 47 kΩ; lower VCEO (30 V); not AEC-Q101 qualified. | Suitable for consumer-grade 5 V systems only; insufficient for 24 V industrial or automotive supply rails. | Choose for cost-sensitive non-automotive designs where 30 V rating and absence of automotive qualification are acceptable. |
Compared with NSVD20011MUTBG and EMX11T2R, PUMD12/DG/B3,115 uniquely delivers matched NPN/PNP operation in one AEC-Q101-qualified SC-88 package with 50 V rating and 47 kΩ precision biasing-making it optimal for space-limited, safety-critical dual-polarity interface tasks.
Availability
PUMD12/DG/B3,115 is available at Aetrix Electronics and suitable for automotive body electronics, industrial programmable logic controllers, and USB-C power delivery systems requiring stable component supply and long-term lifecycle support.
Supply support for PUMD12/DG/B3,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global leader in high-volume production of discrete semiconductors, specializing in automotive-qualified logic, power MOSFETs, and resistor-equipped transistors with manufacturing sites in Europe, Asia, and the Americas.
PUMD12 belongs to Nexperia's RET family designed specifically for reducing component count and simplifying digital interface design in automotive and industrial control applications where reliability and miniaturization are critical.
FAQ
What is the maximum operating temperature for continuous 100 mA output current?
The PUMD12/DG/B3,115 supports 100 mA per transistor continuously up to +85 °C ambient temperature when mounted on a standard FR4 PCB with single-sided copper. At higher temperatures, derating applies per the 417 K/W junction-to-ambient thermal resistance curve shown in Figure 1.
Can Pins 1 and 4 be connected to different ground domains?
Yes-Pins 1 (TR1 emitter) and 4 (TR2 emitter) are electrically isolated internal nodes. They may be connected to separate ground planes (e.g., analog vs. digital) to prevent noise coupling, provided each has a low-impedance return path to its respective supply rail.
Is the R1/R2 ratio guaranteed over temperature?
Yes-the R2/R1 ratio is specified from 0.8 to 1.2 across −65 °C to +150 °C junction temperature, ensuring stable switching thresholds in automotive under-hood environments where thermal drift could otherwise cause logic misstates.
Does this part support wave soldering?
No-reflow soldering is the only recommended process per Section 11 of the datasheet. Wave soldering is explicitly excluded due to thermal stress risks on the ultra-thin leadframe and internal die attach; use only JEDEC-compliant reflow profiles for SOT363 packages.
PUMD12/DG/B3,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Transistor Type:
- 1 NPN, 1 PNP - Pre-Biased (Dual)
- Current - Collector (Ic) (Max):
- 100mA
- Voltage - Collector Emitter Breakdown (Max):
- 50V
- Resistor - Base (R1):
- 47kOhms
- Resistor - Emitter Base (R2):
- 47kOhms
- DC Current Gain (hFE) (Min) @ Ic, Vce:
- 80 @ 5mA, 5V
- Vce Saturation (Max) @ Ib, Ic:
- 150mV @ 500µA, 10mA
- Current - Collector Cutoff (Max):
- 1µA
- Frequency - Transition:
- 230MHz, 180MHz
- Power - Max:
- 300mW
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSSOP
PUMD12/DG/B3,115 FAQ
1.How can I place an order for PUMD12/DG/B3,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PUMD12/DG/B3,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PUMD12/DG/B3,115 reliable?
The price and inventory of PUMD12/DG/B3,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PUMD12/DG/B3,115 is usually 5 days.
3.What payment methods are accepted for PUMD12/DG/B3,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PUMD12/DG/B3,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PUMD12/DG/B3,115?
PUMD12/DG/B3,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PUMD12/DG/B3,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PUMD12/DG/B3,115?
For technical support, including PUMD12/DG/B3,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PUMD12/DG/B3,115 requirements.
6.How does Aetrix verify that PUMD12/DG/B3,115 is sourced from the original manufacturer or authorized distributors?
All PUMD12/DG/B3,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PUMD12/DG/B3,115 meets industry standards.
7.What is the process for return or replacement of PUMD12/DG/B3,115?
All PUMD12/DG/B3,115 units undergo pre-shipment inspection (PSI). If there is an issue with PUMD12/DG/B3,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PUMD12/DG/B3,115 part is unused and in its original packaging.
Return procedure for PUMD12/DG/B3,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PUMD12/DG/B3,115 Tags
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SMUN5311DW1T1G
onsemi
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UMH9NTN
Rohm Semiconductor
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PUMH13,115
Nexperia USA Inc.
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PUMD3-QX
Nexperia USA Inc.
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PUMD2,115
Nexperia USA Inc.
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RN4987FE,LF(CT
Toshiba Semiconductor and Storage
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PUMD12,115
Nexperia USA Inc.
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PUMD9,115
Nexperia USA Inc.
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PUMH9,115
Nexperia USA Inc.
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PUMD3,115
Nexperia USA Inc.
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DCX114EU-7-F
Diodes Incorporated
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PUMD13,115
Nexperia USA Inc.
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