Nexperia USA Inc. PUMD12-QF

Overview

PUMD12-QF from Nexperia is an NPN/PNP resistor-equipped double transistor (RET) in SOT363-3 (SC-88) package, integrating two matched bias networks (R1 = R2 = 47 kΩ) for direct logic-level drive. It delivers 100 mA per transistor, supports ±50 V V_CEO, and is AEC-Q101 qualified for automotive signal conditioning and digital interface control.

For engineers reviewing the PUMD12-QF datasheet, PUMD12-QF pinout, PUMD12-QF application, or PUMD12-QF equivalent, this device serves as a space- and BOM-optimized replacement for discrete NPN+PNP pairs in level-shifting, IC input control, and low-current peripheral driver circuits where built-in biasing eliminates external resistors.

Technical Context

This dual RET integrates one NPN (TR1) and one PNP (TR2) transistor with identical 47 kΩ input bias resistors (R1) and unity R2/R1 ratio, enabling symmetrical on/off thresholds (V_I(on) = 1.6–3 V, V_I(off) = 0.8–1.2 V) and consistent saturation behavior (V_CE(sat) ≤ 100 mV at I_C = 10 mA).

Its thermal design targets 417 K/W junction-to-ambient resistance on FR4 PCBs, supporting continuous 100 mA operation within T_j ≤ 150 °C limits, while f_T values of 230 MHz (NPN) and 180 MHz (PNP) confirm suitability for high-speed digital switching up to ~10 MHz edge rates.

Key Specifications

Pinout & Package

SOT363-3 (TSSOP6) plastic surface-mount package: 1.35 mm × 2.2 mm footprint, 0.65 mm pitch, 0.95 mm max height, optimized for automated placement and reflow soldering on standard FR4 PCBs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-polarity resistor-equipped transistor applications.

Compared with PUMH2 and PUMB2, PUMD12-QF uniquely supports true complementary switching in one package - enabling compact push-pull, level-shifting, and bidirectional interface designs that neither NPN-only nor PNP-only RETs can replicate without additional components.

Availability

PUMD12-QF is available at Aetrix Electronics and suitable for automotive body electronics, industrial PLC I/O modules, and consumer appliance control panels requiring stable component supply and AEC-Q101 compliance.

Supply support for PUMD12-QF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in automotive-qualified components and advanced packaging.

PUMD12-QF belongs to Nexperia's Resistor-Equipped Transistor (RET) family, engineered specifically to reduce component count and improve assembly yield in automotive and industrial digital interface applications.

FAQ

What is the maximum operating temperature for PUMD12-QF in continuous use?

The PUMD12-QF has a maximum junction temperature (T_j) of 150 °C and operates continuously from −40 °C to +125 °C ambient. Its thermal resistance is 417 K/W (per device on FR4 PCB), allowing full 100 mA output current at up to +85 °C ambient without derating when mounted per recommended footprint.

Can PUMD12-QF replace discrete NPN+PNP transistor pairs in existing designs?

Yes - PUMD12-QF replaces two SOT23 transistors plus four bias resistors. Pin compatibility requires layout adaptation to SOT363-3, but electrical behavior matches standard RET operation: I1/O1 form NPN channel, I2/O2 form PNP channel, with GND1 and GND2 serving distinct emitter references.

Does PUMD12-QF require external pull-up or pull-down resistors?

No - each input (I1, I2) includes a 47 kΩ internal resistor to its respective emitter (GND1 or GND2), providing automatic turn-off when the driving signal is high-impedance or floating. This eliminates external biasing components in most digital interface applications.

How does the R2/R1 = 1 ratio affect switching performance?

The unity R2/R1 ratio ensures matched input impedance and symmetric V_I(on)/V_I(off) thresholds (1.6–3 V / 0.8–1.2 V) between NPN and PNP channels, enabling precise timing alignment in push-pull or complementary logic stages without skew-induced shoot-through risk.