Nexperia USA Inc. PUMD12-QX

Overview

PUMD12-QX from Nexperia is an NPN/PNP resistor-equipped double transistor (RET) in SOT363-3 (SC-88) package, featuring integrated 47 kΩ input bias resistors (R1 = R2) per transistor, 50 V V_CEO, 100 mA output current, and AEC-Q101 qualification for automotive signal-level switching in space-constrained control interfaces.

For engineers reviewing the PUMD12-QX datasheet, PUMD12-QX pinout, PUMD12-QX application, or PUMD12-QX equivalent, this device serves as a dual-channel logic-level driver with built-in biasing-ideal for reducing component count in low-current peripheral interface circuits where thermal derating, input voltage thresholds (V_I(on) = 1.6–3 V), and junction temperature limits (T_j ≤ 150 °C) are critical selection criteria.

Technical Context

This dual RET integrates one NPN and one PNP silicon transistor on a single die, each with matched 47 kΩ input resistors and unity R2/R1 ratio, enabling direct TTL/CMOS-compatible drive without external base resistors. The complementary topology supports push-pull or level-shifting configurations in bidirectional digital control paths.

Thermal performance is defined for FR4 PCB mounting: per-device R_th(j-a) = 417 K/W and P_tot = 300 mW at T_amb ≤ 25 °C, with linear derating above 25 °C. Electrical behavior is characterized across –40 °C to +150 °C ambient, including h_FE ≥ 80 (NPN, I_C = 5 mA), f_T = 230 MHz (NPN) and 180 MHz (PNP), and C_c ≤ 3 pF.

Key Specifications

Pinout & Package

SOT363-3 (TSSOP6) plastic surface-mounted package: 2.2 mm × 1.35 mm footprint, 0.65 mm pitch, 0.95 mm max height, lead-free and RoHS-compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual RET applications.

Compared with PUMH2 and PUMB2, PUMD12-QX uniquely delivers matched NPN/PNP functionality in one package-enabling compact, self-contained digital interface stages without topology compromise or additional bias components.

Availability

PUMD12-QX is available at Aetrix Electronics and suitable for automotive body control modules, industrial PLC input stages, consumer appliance UI panels, and medical diagnostic equipment interfaces requiring stable component supply and long-term lifecycle support.

Supply support for PUMD12-QX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable discrete and logic devices for automotive, industrial, and consumer markets.

PUMD12-QX belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to simplify digital interface design in space- and cost-sensitive applications while meeting stringent automotive reliability standards.

FAQ

What is the maximum operating temperature for PUMD12-QX in continuous operation?

The junction temperature must not exceed 150 °C under any operating condition. With R_th(j-a) = 417 K/W on FR4 PCB, ambient temperature must be limited to ≤75 °C at full 300 mW dissipation. Derating curves in the datasheet specify linear reduction above 25 °C ambient.

Can PUMD12-QX be used in 1.8 V logic systems?

Yes. V_I(on) ranges from 1.6 V to 3.0 V, ensuring reliable turn-on with 1.8 V CMOS outputs. At 1.8 V input, typical I_B ≈ 38 µA yields I_C ≈ 3 mA (h_FE ≥ 80), sufficient for LED driving or logic input conditioning.

Is there crosstalk between the NPN and PNP channels?

No measurable electrical crosstalk exists between TR1 (NPN) and TR2 (PNP). They share only the package substrate; isolation exceeds 100 MΩ at 50 V, and thermal coupling is negligible below 100 mW total dissipation per device.

How does the R2/R1 ratio affect switching behavior?

The R2/R1 ratio of 1.0 ±0.2 ensures matched input impedance and threshold symmetry between channels. This enables precise timing alignment in push-pull configurations and prevents shoot-through during transitions in level-shifting applications.