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Nexperia USA Inc. PUMD12/ZLF
- Part No.:
- PUMD12/ZLF
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Bipolar Transistor Arrays, Pre-Biased
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
PUMD12/ZLF.pdf
- Description:
- TRANS PREBIAS
- Quantity:
- Payment:
- Shipping:
Inventory:4,851
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Product details
Overview
PUMD12/ZLF from Nexperia is an NPN/PNP dual resistor-equipped transistor (RET) in a 6-pin SOT363 (SC-88) surface-mount package, integrating matched bias resistors (R1 = R2 = 47 kΩ) for both transistors. It delivers 100 mA output current per channel, supports ±40 V input voltage ranges, and is AEC-Q101 qualified for automotive signal-level switching applications such as LED driver control and logic-level translation.
For engineers reviewing the PUMD12/ZLF datasheet, PUMD12/ZLF pinout, PUMD12/ZLF application, or PUMD12/ZLF equivalent, this page provides verified pin functions, thermal derating curves, DC current gain (hFE ≥ 80 at IC = 5 mA), saturation voltage (VCEsat ≤ 150 mV), and validated alternatives for discrete logic interface consolidation.
Technical Context
The PUMD12/ZLF integrates two complementary silicon transistors - one NPN (TR1) and one PNP (TR2) - each with built-in base bias resistors (R1 = 47 kΩ, R2 = 47 kΩ, ratio 0.8–1.2). Its dual-channel configuration enables push-pull or complementary switching without external bias networks.
It operates across −65 °C to +150 °C ambient temperature, features 50 V collector-emitter breakdown (VCEO), 100 nA collector-base leakage (ICBO), and transition frequencies of 230 MHz (TR1) and 180 MHz (TR2), supporting high-speed digital interface and low-power peripheral driving.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCEO | 50 V - Maximum safe collector-emitter voltage before breakdown; enables use in 24 V automotive and industrial logic interfaces. |
| IO | 100 mA - Continuous output current per transistor; sufficient for driving LEDs, small relays, or MCU I/O buffers. |
| R1 / R2 | 47 kΩ ±22% - Integrated base bias resistors eliminate two external components per channel, reducing BOM count and PCB area. |
| hFE | ≥80 at IC = 5 mA - Ensures reliable saturation with low base drive current, simplifying microcontroller GPIO interfacing. |
| VCEsat | ≤150 mV at IC = 10 mA, IB = 0.5 mA - Minimizes conduction loss and self-heating in always-on or pulsed switching roles. |
| fT | 230 MHz (TR1), 180 MHz (TR2) - Supports >10 MHz digital signal switching, suitable for clock buffering and fast logic level translation. |
| Ptot | 300 mW per device - Total power dissipation limit at Tamb ≤ 25 °C; requires thermal derating above 25 °C per published curve. |
Pinout & Package
SOT363 (SC-88) ultra-small plastic surface-mount package: 2.2 mm × 1.35 mm × 0.95 mm body, 0.65 mm lead pitch, 6-terminal configuration with gull-wing leads.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | GND (emitter of TR1) | Common emitter reference for NPN transistor; connects to system ground or low-side return path. |
| 2 | Input (base of TR1) | Direct logic-level input to NPN base via internal R1; accepts 0–40 V positive signals. |
| 3 | Output (collector of TR2) | Active-high output node driven by PNP transistor; sinks current when TR2 is on. |
| 4 | GND (emitter of TR2) | Common emitter reference for PNP transistor; ties to system ground or shared emitter node. |
| 5 | Input (base of TR2) | Direct logic-level input to PNP base via internal R1; accepts −40 V to 0 V negative signals. |
| 6 | Output (collector of TR1) | Active-low output node driven by NPN transistor; sources current when TR1 is on. |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q101 qualification | Validated for automotive-grade reliability including temperature cycling, HTRB, and ESD testing - suitable for under-hood and ADAS subsystems. |
| Integrated R1/R2 bias network | Eliminates four external resistors in typical inverter or level-shifter designs, reducing placement time and solder joint count. |
| Complementary NPN+PNP pairing | Enables single-package push-pull output stages without cross-conduction risk, ideal for driving capacitive loads like bus lines or gate drivers. |
| Low VI(on)/VI(off) thresholds | On-state input voltage ≤1.6 V (TR1), ≤−1.6 V (TR2); off-state threshold ≥1.2 V (TR1), ≥−1.2 V (TR2) - ensures clean logic-level recognition with 3.3 V/5 V MCUs. |
| Thermal resistance (Rth(j-a)) | 417 K/W per device on FR4 PCB - enables stable operation up to +100 °C ambient with no heatsink required in low-duty-cycle applications. |
Applications
| Automotive LED Signaling | Industrial PLC Input Conditioning |
|---|---|
|
Use Scenario: Driving amber turn-signal LEDs from 12 V vehicle battery with PWM dimming control. IC Role / Device Role: Dual-channel level translator and current switch - TR1 sinks LED cathode current; TR2 sources auxiliary status indicator current. Use Value: Built-in 47 kΩ bias resistors allow direct connection to 3.3 V microcontroller GPIO without external pull-ups/downs, reducing component count by 4 per channel. |
Use Scenario: Converting 24 V DC field sensor outputs to 3.3 V logic levels for ARM-based controller inputs. IC Role / Device Role: High-side and low-side interface buffer - TR2 switches 24 V input to GND-referenced logic; TR1 provides inverted enable path. Use Value: 50 V VCEO rating and −40 V to +40 V input tolerance ensure robust operation against load dump transients and reverse polarity events. |
| Consumer Appliance Control Panel | Medical Diagnostic Equipment I/O Isolation |
|
Use Scenario: Debouncing tactile switch inputs and driving bi-color status indicators in smart home hubs. IC Role / Device Role: Dual-function signal conditioner - TR1 acts as Schmitt-trigger input buffer; TR2 drives common-anode RGB LED segments. Use Value: Matched hFE (≥80) and VCEsat (≤150 mV) across both transistors guarantee consistent brightness and response timing across color channels. |
Use Scenario: Galvanically isolated digital signal routing between patient-connected analog front-end and main processor board. IC Role / Device Role: Low-power logic-level translator in optocoupler driver stage - TR1 drives opto-LED anode; TR2 provides feedback path. Use Value: 100 nA ICBO and 1 µA ICEO at 25 °C minimize standby current leakage, critical for battery-backed diagnostic runtime compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual RET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NSVD2101PT1G | PNP/NPN RET in SOT-563; R1 = R2 = 100 kΩ; VCEO = 50 V; IO = 100 mA; fT = 150 MHz (PNP), 200 MHz (NPN) | Higher bias resistance increases input impedance but reduces switching speed; lower fT limits use in >5 MHz clocked interfaces. | Select when higher input impedance is needed and speed is secondary; verify VI(on)/VI(off) compatibility with host logic family. |
| EMX11T2R | NPN+NPN RET in SOT-363; R1 = R2 = 47 kΩ; VCEO = 50 V; IO = 100 mA; hFE = 80–250; no PNP channel | Lacks complementary output capability - unsuitable for push-pull or active-high/active-low dual-drive topologies. | Choose only for NPN-only applications requiring identical biasing; not a functional replacement for PUMD12/ZLF's complementary pair. |
Compared with NSVD2101PT1G and EMX11T2R, PUMD12/ZLF uniquely offers matched 47 kΩ biasing, balanced NPN/PNP fT performance (230/180 MHz), and true complementary output architecture - making it the only option among the three capable of single-package bidirectional logic translation with minimal external components.
Availability
PUMD12/ZLF is available at Aetrix Electronics and suitable for automotive lighting control, industrial PLC input conditioning, and consumer appliance interface design requiring stable component supply and AEC-Q101 compliance.
Supply support for PUMD12/ZLF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global leader in high-volume production of discrete semiconductors, acquired from NXP's Standard Products division in 2017 and focused on automotive, industrial, and computing markets.
The PUMD12/ZLF belongs to Nexperia's Resistor-Equipped Transistor (RET) portfolio, engineered specifically to replace discrete transistor-resistor combinations in space-constrained, high-reliability digital interface applications.
FAQ
What is the maximum allowable junction temperature for PUMD12/ZLF?
The absolute maximum junction temperature (Tj) is 150 °C, as defined in the limiting values table. Operation beyond this temperature risks permanent parametric shift or failure. Derating begins at Tamb > 25 °C per the published 417 K/W thermal resistance curve, requiring power reduction of ~1.2 mW/°C above ambient.
Can PUMD12/ZLF be used in a single-supply 3.3 V system?
Yes - its VI(on) threshold is ≤1.6 V for TR1 and ≤−1.6 V for TR2, enabling reliable turn-on with standard 3.3 V CMOS logic outputs. The 47 kΩ internal bias resistors provide appropriate base current for 100 mA output while maintaining margin against overdrive.
Is wave soldering recommended for PUMD12/ZLF?
No - reflow soldering is the only recommended method per Section 11 of the datasheet. Wave soldering is explicitly discouraged due to thermal stress on the SOT363 package; Figure 20 shows a wave footprint only for legacy reference, not endorsement.
How does the R2/R1 ratio affect switching behavior?
The R2/R1 ratio of 0.8–1.2 ensures matched base current scaling between TR1 and TR2, minimizing propagation delay mismatch (<5 ns typical) in complementary switching. Deviations outside this range cause asymmetrical rise/fall times and increased shoot-through risk in push-pull configurations.
PUMD12/ZLF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Transistor Type:
- 1 NPN, 1 PNP - Pre-Biased (Dual)
- Current - Collector (Ic) (Max):
- 100mA
- Voltage - Collector Emitter Breakdown (Max):
- 50V
- Resistor - Base (R1):
- 47kOhms
- Resistor - Emitter Base (R2):
- 47kOhms
- DC Current Gain (hFE) (Min) @ Ic, Vce:
- 80 @ 5mA, 5V
- Vce Saturation (Max) @ Ib, Ic:
- 150mV @ 500µA, 10mA
- Current - Collector Cutoff (Max):
- 1µA
- Frequency - Transition:
- 230MHz, 180MHz
- Power - Max:
- 300mW
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSSOP
PUMD12/ZLF FAQ
1.How can I place an order for PUMD12/ZLF through Aetrix?
Please submit a Request for Quotation (RFQ) for PUMD12/ZLF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PUMD12/ZLF reliable?
The price and inventory of PUMD12/ZLF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PUMD12/ZLF is usually 5 days.
3.What payment methods are accepted for PUMD12/ZLF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PUMD12/ZLF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PUMD12/ZLF?
PUMD12/ZLF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PUMD12/ZLF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PUMD12/ZLF?
For technical support, including PUMD12/ZLF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PUMD12/ZLF requirements.
6.How does Aetrix verify that PUMD12/ZLF is sourced from the original manufacturer or authorized distributors?
All PUMD12/ZLF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PUMD12/ZLF meets industry standards.
7.What is the process for return or replacement of PUMD12/ZLF?
All PUMD12/ZLF units undergo pre-shipment inspection (PSI). If there is an issue with PUMD12/ZLF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PUMD12/ZLF part is unused and in its original packaging.
Return procedure for PUMD12/ZLF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PUMD12/ZLF Tags
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SMUN5311DW1T1G
onsemi
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UMH9NTN
Rohm Semiconductor
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PUMH13,115
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PUMH9,115
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