Nexperia USA Inc. PUMD13,135

Overview

PUMD13 from Nexperia is an NPN/PNP resistor-equipped double transistor (RET) in SOT363-3 (SC-88) package, rated for 50 V V_CEO, 100 mA output current per transistor, with integrated bias resistors R1 = 4.7 kΩ and R2 = 47 kΩ. It functions as a dual-channel digital switching element for level translation and IC input control in space-constrained logic interfaces.

For engineers reviewing the PUMD13 datasheet, PUMD13 pinout, PUMD13 application, or PUMD13 equivalent, this device serves as a compact, bias-resistor-integrated replacement for discrete NPN+PNP pairs in low-current peripheral drivers, reducing PCB area and assembly cost while maintaining predictable DC gain (h_FE ≥ 100 at I_C = 10 mA) and low saturation voltage (V_CE(sat) ≤ 100 mV).

Technical Context

The PUMD13 integrates two complementary bipolar transistors - TR1 (NPN) and TR2 (PNP) - each with dedicated on-chip base bias networks (R1 and R2). The R2/R1 ratio is tightly controlled at 10 ± 2, enabling consistent turn-on behavior across temperature (−40 °C to +150 °C junction).

Each transistor operates independently with separate emitter (GND1/GND2), base (I1/I2), and collector (O1/O2) terminals. The device supports bidirectional signal conditioning: TR1 handles positive-input logic drive, TR2 handles negative-input or inverted-level applications, with VI(on) = 0.9–1.3 V (TR1) and VI(on) = −0.9 to −1.3 V (TR2) under defined test conditions.

Key Specifications

Pinout & Package

SOT363-3 (TSSOP6) plastic surface-mounted package: 2.2 mm × 1.35 mm footprint, 0.65 mm pitch, 0.95 mm max height, FR4-compatible reflow profile.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar resistor-equipped transistor applications.

Compared with PUMB13 and PUMH13, the PUMD13 uniquely provides complementary NPN/PNP functionality in one package - enabling true push-pull output stages without cross-coupling or external inversion, which reduces interconnect delay and improves noise immunity in mixed-signal interfaces.

Availability

PUMD13 is available at Aetrix Electronics and suitable for industrial sensor interfaces, microcontroller GPIO expansion, LED driver circuits, and legacy bus level translation requiring stable component supply and long-term manufacturability.

Supply support for PUMD13 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and efficient logic, discrete, and MOSFET solutions for automotive, industrial, mobile, and computing markets.

The PUMD13 belongs to Nexperia's Resistor-Equipped Transistor (RET) family, engineered specifically to replace discrete transistor-resistor combinations in digital interface and peripheral driver applications - prioritizing miniaturization, assembly efficiency, and parametric consistency.

FAQ

What is the maximum allowable continuous power dissipation for PUMD13?

The PUMD13 has a per-device total power dissipation limit of 300 mW at T_amb ≤ 25 °C on FR4 PCB with single-sided copper. Derating begins above 25 °C at 4.8 mW/°C (1/417 K/W), reaching 0 mW at 95 °C ambient. This rating assumes both transistors operate simultaneously under worst-case V_CE and I_C conditions.

Can PUMD13 be used with 1.8 V logic inputs?

No - the VI(on) threshold for TR1 is specified at 0.9–1.3 V (typ/max) at I_C = 5 mA, but guaranteed turn-on requires ≥1.3 V. At 1.8 V, margin is insufficient for reliable operation across temperature and process variation; use PUMD3 or PUMD6 for 1.8 V compatibility.

How are the internal resistors R1 and R2 physically arranged?

R1 connects between each input pin (I1/I2) and its respective transistor base; R2 connects between base and emitter (GND1/GND2). This forms a classic two-resistor bias network per transistor, with no shared nodes - confirmed by Figure 15 and 16 in the datasheet and verified via electrical testing per Table 8.

Is thermal resistance measured per transistor or for the entire device?

R_th(j-a) is specified both ways: 625 K/W per transistor (junction-to-ambient, individual die), and 417 K/W per device (combined thermal path from either junction to ambient). The lower per-device value reflects shared heat spreading through the common leadframe and package mold compound.