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Nexperia USA Inc. PUMD13/ZLF
- Part No.:
- PUMD13/ZLF
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Bipolar Transistor Arrays, Pre-Biased
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
PUMD13/ZLF.pdf
- Description:
- TRANS PREBIAS
- Quantity:
- Payment:
- Shipping:
Inventory:2,354
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Product details
Overview
PUMD13/ZLF from Nexperia is an NPN/PNP resistor-equipped double transistor (RET) in SOT363-3 (SC-88) package, rated for 50 V VCEO, 100 mA output current per transistor, with integrated bias resistors R1 = 4.7 kΩ and R2 = 47 kΩ. It serves as a compact, dual-polarity logic-level switch for digital interface buffering and low-power peripheral control in space-constrained PCBs.
For engineers reviewing the PUMD13/ZLF datasheet, PUMD13/ZLF pinout, PUMD13/ZLF application, or PUMD13/ZLF equivalent, this device offers verified dual-transistor functionality with built-in biasing-enabling direct TTL/CMOS drive without external resistors while maintaining discrete transistor behavior and thermal derating compliance on FR4 PCBs.
Technical Context
The PUMD13/ZLF integrates two monolithically isolated transistors: TR1 (NPN) and TR2 (PNP), each with dedicated base bias networks. Its internal R1–R2 configuration sets fixed current gain control (R2/R1 = 10 typ), enabling predictable saturation at IC/IB = 20 across –40 °C to +100 °C.
Each transistor operates independently with separate emitter grounds (GND1, GND2), collector outputs (O1, O2), and base inputs (I1, I2). The device supports bidirectional level translation via complementary switching-TR1 sinks current when I1 exceeds VI(on) ≈ 0.9 V, while TR2 sources current when I2 falls below VI(on) ≈ –0.9 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCEO | 50 V max per transistor - defines safe switching voltage for 3.3 V/5 V logic-driven loads without breakdown risk |
| IO | 100 mA max per transistor - supports driving LEDs, small relays, or logic inputs without external current limiting |
| R1 | 4.7 kΩ ±28% - sets input current limit (~1 mA at 5 V), eliminating need for external base resistor |
| R2/R1 | 10 typ - ensures stable hFE-independent biasing for consistent saturation under varying temperature |
| VCE(sat) | 100 mV max at IC = 5 mA, IB = 0.25 mA - enables low-loss switching in battery-powered signal paths |
| fT | 230 MHz (TR1), 180 MHz (TR2) - supports high-speed digital switching up to ~10 MHz with minimal propagation delay |
| Ptot | 300 mW per device at Tamb ≤ 25 °C - requires thermal derating above 25 °C per 417 K/W junction-to-ambient resistance |
Pinout & Package
SOT363-3 (TSSOP6) plastic surface-mounted package: 1.3 mm × 2.2 mm footprint, 0.65 mm pitch, 0.95 mm max height, designed for reflow soldering on FR4 PCBs with single-sided 35 µm copper.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | GND1 | Emitter connection for TR1 (NPN); must be tied to system ground or low-side reference |
| 2 | I1 | Base input for TR1 (NPN); accepts positive logic signals (0.6–1.3 V threshold range) |
| 3 | O2 | Collector output for TR2 (PNP); sources current when I2 is pulled low |
| 4 | GND2 | Emitter connection for TR2 (PNP); independent of GND1, allows floating or split-rail biasing |
| 5 | I2 | Base input for TR2 (PNP); accepts negative logic signals (–0.5 to –0.6 V off-state, –0.9 V on-state) |
| 6 | O1 | Collector output for TR1 (NPN); sinks current when I1 is driven high |
Key Features
| Feature | Design Value |
|---|---|
| Dual polarity integration | NPN + PNP pair in one SOT363-3 package reduces board area by >40% vs. discrete equivalents |
| Built-in bias network | Fixed R1 = 4.7 kΩ and R2 = 47 kΩ eliminate four external resistors and associated layout error risk |
| Thermal robustness | 150 °C max junction temperature and 417 K/W per-device Rth(j-a) support continuous operation in industrial ambient (85 °C) |
| Input voltage tolerance | I1 withstands +30 V transient; I2 withstands –30 V transient - enables direct connection to unregulated rails |
| Low leakage performance | ICEO ≤ 5 µA at 150 °C ensures reliable off-state isolation in high-temperature sensor interfaces |
Applications
| LED Driver Interface | Microcontroller GPIO Expander |
|---|---|
|
Use Scenario: Driving dual-color (red/green) LED indicators from a single 3.3 V MCU port with active-high and active-low control. IC Role / Device Role / Timing Role: TR1 sinks current for red LED (active-high), TR2 sources current for green LED (active-low), sharing one GPIO pin via complementary logic. Use Value: Eliminates need for two discrete transistors and four bias resistors; reduces BOM count by 6 parts and saves 2.5 mm² PCB area. |
Use Scenario: Extending limited GPIO count on an ARM Cortex-M0+ MCU to control six independent enable lines for peripheral ICs. IC Role / Device Role / Timing Role: Each PUMD13/ZLF provides two independent switch channels; three devices deliver six buffered, level-shifted outputs from three MCU pins. Use Value: Enables full rail-to-rail switching (0–5 V) without level shifters; maintains <100 ns propagation delay for synchronous peripheral enable timing. |
| Logic-Level Translator | Low-Power Sensor Interface |
|
Use Scenario: Bidirectional voltage translation between 1.8 V FPGA I/O banks and 5 V legacy sensor modules using open-drain signaling. IC Role / Device Role / Timing Role: TR1 acts as pull-down for 1.8 V side; TR2 acts as pull-up for 5 V side, forming a passive translator with controlled rise/fall times. Use Value: Achieves sub-µs edge transitions without external pull-ups; eliminates shoot-through risk due to separated emitter grounds. |
Use Scenario: Enabling/disabling analog sensor power rails (e.g., Hall-effect or thermistor circuits) in battery-operated IoT nodes. IC Role / Device Role / Timing Role: TR1 controls VCC enable path (low-side switch); TR2 controls REF voltage path (high-side switch), both synchronized by same control signal. Use Value: Reduces quiescent current to <1 µA in sleep mode via guaranteed cutoff (VI(off) ≤ 0.6 V), extending battery life by >30%. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar resistor-equipped transistor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PUMB13 | PNP/PNP complement - identical R1/R2 values but dual-PNP topology | Required only when both outputs must source current (e.g., dual high-side switches) | Select when matching PNP-only load requirements; not interchangeable for NPN/PNP mixed use cases |
| PUMH13 | NPN/NPN complement - identical R1/R2 values but dual-NPN topology | Required only when both outputs must sink current (e.g., dual low-side drivers) | Select when driving two grounded loads; incompatible with high-side or rail-to-rail configurations |
Compared with PUMB13 and PUMH13, the PUMD13/ZLF uniquely supports complementary switching in a single package-enabling push-pull-like behavior without cross-conduction risk, making it the only choice for mixed-sourcing/sinking applications like LED polarity control or bidirectional level translation.
Availability
PUMD13/ZLF is available at Aetrix Electronics and suitable for LED driver interfaces, microcontroller GPIO expansion, logic-level translation, and low-power sensor interface applications requiring stable component supply, consistent parametric performance, and long-term industrial lifecycle support.
Supply support for PUMD13/ZLF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability essential semiconductors for automotive, industrial, and consumer markets.
The PUMD13/ZLF belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to reduce component count and improve assembly yield in digital interface and peripheral driver circuits.
FAQ
What is the maximum allowable input voltage at I1 and I2 pins?
The I1 pin tolerates +30 V transient input voltage, while I2 tolerates –30 V transient input voltage, per Absolute Maximum Ratings. Continuous DC operation is specified up to +5 V for I1 and –5 V for I2. These limits ensure robustness against ESD and supply rail overshoot in industrial environments without external clamping.
Can PUMD13/ZLF replace two individual BC847/BC857 transistors in a design?
Yes, but only when bias resistor values match the internal R1 = 4.7 kΩ and R2 = 47 kΩ network. Unlike discrete transistors, PUMD13/ZLF fixes base current and gain ratio, eliminating tuning flexibility but guaranteeing consistent saturation and reducing layout complexity. Thermal coupling between TR1 and TR2 also differs from physically separated devices.
How does the dual-emitter isolation (GND1/GND2) affect circuit design?
GND1 and GND2 are electrically isolated terminals, allowing TR1 and TR2 to operate with different reference potentials-e.g., TR1 referenced to digital ground and TR2 referenced to analog ground or a negative rail. This prevents ground loop interference and enables true bidirectional level translation without shared emitter constraints.
Is PUMD13/ZLF qualified for automotive applications?
No. PUMD13/ZLF is not AEC-Q101 qualified and lacks automotive-grade screening, temperature range extension (–40 °C to +125 °C), or stress test validation. It is intended for industrial and consumer applications with ambient operating temperatures up to +85 °C. Automotive designs require explicitly qualified alternatives such as Nexperia's PMMD13 series.
PUMD13/ZLF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Transistor Type:
- 1 NPN, 1 PNP - Pre-Biased (Dual)
- Current - Collector (Ic) (Max):
- 100mA
- Voltage - Collector Emitter Breakdown (Max):
- 50V
- Resistor - Base (R1):
- 4.7kOhms
- Resistor - Emitter Base (R2):
- 47kOhms
- DC Current Gain (hFE) (Min) @ Ic, Vce:
- 100 @ 10mA, 5V
- Vce Saturation (Max) @ Ib, Ic:
- 100mV @ 250µA, 5mA
- Current - Collector Cutoff (Max):
- 1µA
- Frequency - Transition:
- 230MHz, 180MHz
- Power - Max:
- 300mW
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSSOP
PUMD13/ZLF FAQ
1.How can I place an order for PUMD13/ZLF through Aetrix?
Please submit a Request for Quotation (RFQ) for PUMD13/ZLF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PUMD13/ZLF reliable?
The price and inventory of PUMD13/ZLF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PUMD13/ZLF is usually 5 days.
3.What payment methods are accepted for PUMD13/ZLF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PUMD13/ZLF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PUMD13/ZLF?
PUMD13/ZLF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PUMD13/ZLF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PUMD13/ZLF?
For technical support, including PUMD13/ZLF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PUMD13/ZLF requirements.
6.How does Aetrix verify that PUMD13/ZLF is sourced from the original manufacturer or authorized distributors?
All PUMD13/ZLF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PUMD13/ZLF meets industry standards.
7.What is the process for return or replacement of PUMD13/ZLF?
All PUMD13/ZLF units undergo pre-shipment inspection (PSI). If there is an issue with PUMD13/ZLF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PUMD13/ZLF part is unused and in its original packaging.
Return procedure for PUMD13/ZLF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PUMD13/ZLF Tags
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SMUN5311DW1T1G
onsemi
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UMH9NTN
Rohm Semiconductor
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PUMH13,115
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PUMH9,115
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DCX114EU-7-F
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