Nexperia USA Inc. PUMD15,135

Overview

PUMD15 from Nexperia is an AEC-Q101-qualified NPN/PNP resistor-equipped double transistor (RET) in SOT363-3 (SC-88) package, featuring integrated 4.7 kΩ input bias resistors per transistor, 50 V V_CEO, and 100 mA output current capability - used for bidirectional digital signal interfacing and low-current peripheral control in space-constrained automotive and industrial PCBs.

For engineers reviewing the PUMD15 datasheet, PUMD15 pinout, PUMD15 application, or PUMD15 equivalent, this device serves as a drop-in replacement for discrete NPN+PNP pairs in level-shifting, bus buffering, and IC input conditioning circuits where reduced BOM count and AEC-Q101 reliability are required.

Technical Context

The PUMD15 integrates two monolithically matched transistors - TR1 (NPN) and TR2 (PNP) - each with dedicated on-die base bias networks (R1 = R2 = 4.7 kΩ, ratio = 1.0). Its dual-polarity architecture enables complementary switching without external resistors, supporting push-pull or inverter configurations in 3.3 V/5 V logic domains.

Thermal performance is defined for FR4 PCB mounting: 417 K/W junction-to-ambient (per device), with 300 mW total power dissipation at T_amb ≤ 25 °C. DC current gain (h_FE) ranges from 30 (TR1, I_C = 10 mA) to ≥20 (TR2, |I_C| = 10 mA), and transition frequencies reach 230 MHz (TR1) and 180 MHz (TR2).

Key Specifications

Pinout & Package

SOT363-3 (TSSOP6) plastic surface-mount package: 2.2 mm × 1.35 mm footprint, 0.65 mm pitch, 0.95 mm max height, optimized for reflow soldering with standard 0.5 mm paste apertures.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar resistor-equipped transistor applications.

Compared with PUMH15 and PUMB15, the PUMD15 uniquely delivers matched NPN+PNP functionality in one die - enabling true bidirectional signal control without interposer routing or additional decoupling, making it irreplaceable in compact level translators and dual-mode peripheral interfaces.

Availability

PUMD15 is available at Aetrix Electronics and suitable for automotive body electronics, industrial PLC I/O modules, and consumer IoT gateway designs requiring stable component supply, AEC-Q101 compliance, and ultra-small SMD packaging.

Supply support for PUMD15 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and discrete components - serving automotive, industrial, and mobile markets with ISO/TS 16949-certified manufacturing.

The PUMD15 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to replace discrete transistor-resistor combinations in cost- and space-sensitive digital interface applications.

FAQ

Is PUMD15 pin-compatible with other SOT363-3 RETs like PUMH15 or PUMB15?

Yes - all three share identical SOT363-3 (TSSOP6) pinout and mechanical footprint. However, internal transistor polarity differs: PUMD15 has NPN/PNP, PUMH15 is NPN/NPN, and PUMB15 is PNP/PNP. Swapping requires circuit-level validation of signal direction and bias requirements.

What is the maximum operating temperature for continuous use?

The PUMD15 supports continuous operation from −65 °C to +150 °C ambient, with junction temperature limited to 150 °C. Derating begins above 25 °C ambient: total device power must be reduced linearly to 0 mW at 125 °C ambient per the 417 K/W R_th(j-a) curve.

Can PUMD15 drive a 20 mA LED directly from a 3.3 V GPIO?

Yes - with V_CE(sat) ≤ 150 mV and h_FE ≥ 30, TR1 delivers full 20 mA sink current using ≤0.67 mA base drive. At 3.3 V supply, forward voltage drop across a typical red LED (~1.8 V) leaves 1.35 V across the transistor, well within safe V_CE margin.

Does PUMD15 require external bypass capacitors for stable switching?

No - its integrated bias network and low capacitance (C_c ≤ 3 pF per transistor) ensure stable 10–20 MHz switching without external decoupling. For >50 MHz operation or noisy supply rails, a 100 nF ceramic capacitor between V_CC and GND2 is recommended near the package.