Nexperia USA Inc. PUMD15/ZLX

Overview

PUMD15/ZLX from Nexperia is an AEC-Q101-qualified NPN/PNP resistor-equipped double transistor (RET) in SOT363-3 (SC-88) package, rated for 50 V V_CEO, 100 mA output current per transistor, with integrated bias resistors R1 = R2 = 4.7 kΩ. It serves as a compact, dual-polarity logic-level switch for digital interface buffering and low-current peripheral control in space-constrained automotive and industrial PCBs.

For engineers reviewing the PUMD15/ZLX datasheet, PUMD15/ZLX pinout, PUMD15/ZLX application, or PUMD15/ZLX equivalent, this device supports simplified digital signal inversion, bidirectional level translation, and discrete transistor replacement in I/O expansion circuits-requiring verification of input voltage thresholds (V_I(on) = 1.9 V typ, V_I(off) = 1.1 V typ), saturation behavior (V_CE(sat) ≤ 150 mV), and thermal derating on FR4 PCBs.

Technical Context

The PUMD15/ZLX integrates two monolithically isolated transistors: TR1 (NPN) and TR2 (PNP), each with dedicated base biasing via matched 4.7 kΩ input resistors and unity R2/R1 ratio. Its dual-polarity architecture enables complementary switching without external bias networks, supporting push-pull or totem-pole configurations in digital logic interfaces.

It operates within ±10 V input voltage limits (VI for TR1: −10 to 30 V; VI for TR2: −30 to 10 V), delivers f_T = 230 MHz (TR1) and 180 MHz (TR2), and maintains h_FE ≥ 30 at IC = 10 mA - confirming suitability for high-speed, low-power switching rather than linear amplification.

Key Specifications

Pinout & Package

SOT363-3 (TSSOP6) plastic surface-mounted package: 2.2 mm × 1.35 mm × 0.95 mm body, 0.65 mm lead pitch, gull-wing leads, moisture sensitivity level 1 (MSL1).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-polarity RET applications.

Compared with PUMD15/ZLX, PUMH15 omits PNP functionality entirely - limiting it to unidirectional applications - while NSVD2001MW6T1G trades speed and input matching for higher voltage tolerance, demanding layout and timing validation for reuse in existing designs.

Availability

PUMD15/ZLX is available at Aetrix Electronics and suitable for automotive body electronics, industrial I/O modules, and consumer appliance control panels requiring stable component supply, AEC-Q101 compliance, and compact dual-transistor integration.

Supply support for PUMD15/ZLX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable discrete, logic, and MOSFET solutions for automotive, industrial, and mobile markets.

The PUMD15/ZLX belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to reduce component count and improve reliability in digital interface and low-power switching applications across harsh-environment electronics.

FAQ

What is the maximum ambient temperature for continuous 100 mA operation per transistor?

The PUMD15/ZLX supports continuous 100 mA per transistor up to T_amb = 85 °C when mounted on a standard FR4 PCB with single-sided 35 µm copper, based on its 300 mW total power derating curve (Fig. 1). Above 85 °C, output current must be reduced linearly to maintain junction temperature ≤ 150 °C.

Can PUMD15/ZLX be used in a totem-pole output stage driving a 50 Ω load?

No - the PUMD15/ZLX is not rated for totem-pole output stages driving 50 Ω loads. Its 100 mA I_O limit and 150 mV V_CE(sat) imply a minimum load resistance of ~500 Ω at 5 V supply to avoid exceeding P_tot. For 50 Ω loads, dedicated driver ICs or discrete MOSFETs with higher current capability are required.

How does the R2/R1 = 1.0 ratio affect switching behavior compared to asymmetric RETs?

The unity R2/R1 ratio ensures matched input impedance and identical V_I(on)/V_I(off) thresholds for both transistors, enabling symmetrical rise/fall times in complementary switching. Asymmetric RETs (e.g., R2/R1 = 0.1) skew turn-on bias, causing duty-cycle distortion and increased shoot-through risk in push-pull configurations.

Is the SOT363-3 package compatible with standard 0.65 mm pitch reflow soldering profiles?

Yes - the SOT363-3 package uses 0.65 mm lead pitch and conforms to JEDEC J-STD-020 moisture sensitivity level 1. Its recommended reflow profile matches IPC/JEDEC J-STD-020 Class 1, with peak temperature ≤ 260 °C and time above liquidus 60–150 s, as validated in Nexperia's soldering documentation (Fig. 18–19).