Nexperia USA Inc. PUMD2,125

Overview

PUMD2 from Nexperia is an NPN/PNP resistor-equipped double transistor (RET) in SOT363-3 (SC-88) package, rated for 50 V V_CEO, 100 mA output current per transistor, with integrated 22 kΩ input bias resistors (R1 = R2 = 22 kΩ). It functions as a dual-channel digital switching element for level translation and signal inversion in compact logic interface circuits.

For engineers reviewing the PUMD2 datasheet, PUMD2 pinout, PUMD2 application, or PUMD2 equivalent, this device serves as a space-optimized replacement for discrete NPN+PNP pairs in low-current peripheral drivers, IC input control, and digital logic buffering where bias resistor integration reduces BOM count and layout complexity.

Technical Context

The PUMD2 integrates two complementary bipolar transistors - TR1 (NPN) and TR2 (PNP) - each with monolithically embedded base bias resistors (R1, R2), enabling direct TTL/CMOS-compatible drive without external bias networks. Its dual-transistor topology supports push-pull or complementary switching configurations.

Each transistor operates independently with verified DC current gain (h_FE ≥ 60 at I_C = 5 mA), collector-emitter saturation voltage ≤ 150 mV (I_C = 10 mA), and transition frequencies of 230 MHz (TR1) and 180 MHz (TR2), confirming suitability for medium-speed digital switching up to ~50 MHz.

Key Specifications

Pinout & Package

SOT363-3 (SC-88/TSSOP6) surface-mount plastic package with 6 leads, 0.65 mm pitch, and exposed pad-free construction optimized for automated assembly and reflow soldering.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar resistor-equipped transistor applications.

Compared with PUMH1 and PUMB1, the PUMD2 uniquely provides complementary NPN/PNP functionality in one package - enabling true push-pull operation, bidirectional level translation, and reduced interconnect routing versus using two separate RETs.

Availability

PUMD2 is available at Aetrix Electronics and suitable for LED indicator drivers, microcontroller GPIO expansion, logic-level translation, and push-pull digital output stages requiring stable component supply and consistent parametric performance across production batches.

Supply support for PUMD2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, analog, and discrete devices for automotive, industrial, and consumer markets.

The PUMD2 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered to replace discrete transistor-resistor combinations in digital interface and peripheral driver applications while minimizing PCB area and assembly cost.

FAQ

What is the maximum operating temperature for PUMD2?

The PUMD2 has a specified junction temperature limit of 150 °C and an ambient operating range of −55 °C to +150 °C. Its thermal resistance from junction to ambient is 417 K/W (per device on FR4 PCB), meaning it can dissipate up to 300 mW at 25 °C ambient before reaching T_j = 150 °C - derating applies above 25 °C per the published power curve.

Can PUMD2 be used in analog amplifier configurations?

No - the PUMD2 is designed and characterized exclusively for digital switching applications. Its integrated bias resistors fix the base current path, and parameters like h_FE variation, V_CE(sat), and f_T are specified under saturated switching conditions, not linear amplification. It lacks the bias stability and linearity required for analog gain stages.

How does the R2/R1 ratio affect switching behavior?

The R2/R1 ratio of 0.8–1.2 ensures matched base current scaling between TR1 and TR2, enabling balanced turn-on characteristics in complementary configurations. This tight tolerance maintains consistent V_I(on) and V_I(off) thresholds across temperature, critical for reliable logic-level translation without skew-induced glitches.

Is PUMD2 pin-compatible with other SOT363-3 RETs like PUMH2 or PUMD3?

No - while all share the SOT363-3 mechanical footprint, pin assignments differ significantly. For example, PUMH2 uses pins 1/2 for both NPN emitters and bases, whereas PUMD2 assigns GND1/I1/O1/GND2/I2/O2 across all six pins. Direct substitution requires schematic and layout revision to match functional pin mapping.