Nexperia USA Inc. PUMD2/DG/B3,115

Overview

PUMD2/DG/B3,115 from Nexperia is an NPN/PNP dual resistor-equipped transistor (RET) in a SOT363 (SC-88) surface-mount package, integrating two matched bias resistors (R1 = R2 = 22 kΩ) per transistor pair. It delivers 100 mA output current per channel, supports ±40 V input voltage swing, and is AEC-Q101 qualified for automotive signal-level switching applications such as LED driver control and logic-level translation.

For engineers reviewing the PUMD2/DG/B3,115 datasheet, PUMD2/DG/B3,115 pinout, PUMD2/DG/B3,115 application, or PUMD2/DG/B3,115 equivalent, this page provides verified pin functions, thermal derating curves, DC current gain (hFE ≥ 60 at IC = 5 mA), collector-emitter saturation voltage (VCEsat ≤ 150 mV), and validated alternatives for digital interface consolidation.

Technical Context

The device integrates one NPN and one PNP transistor with built-in base bias resistors (R1 = 22 kΩ, R2 = 22 kΩ, ratio 0.8–1.2), eliminating external bias components. Each transistor operates independently with open-base VCEO = 50 V and IO = 100 mA rating.

It features dual-channel complementary switching capability in a single ultra-small SC-88 footprint, supporting bidirectional level-shifting and push-pull output stages without discrete bias networks. Thermal resistance is 417 K/W (per device) on FR4 PCB, enabling stable operation up to +150 °C junction temperature.

Key Specifications

Pinout & Package

SOT363 (SC-88) 6-pin ultra-small flat lead package, 2.2 mm × 1.35 mm × 0.95 mm body size, with exposed pad not electrically connected.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual RET applications.

Compared with NSVD2T114LT1G and EMX11T2R, PUMD2/DG/B3,115 offers balanced bias (22 kΩ), optimal thermal resistance (417 K/W), and AEC-Q101 validation-making it the default choice for cost-sensitive, thermally constrained automotive and industrial digital interfaces.

Availability

PUMD2/DG/B3,115 is available at Aetrix Electronics and suitable for automotive body electronics, industrial programmable logic controllers, consumer appliance control panels, and medical diagnostic equipment requiring stable component supply and long-term lifecycle support.

Supply support for PUMD2/DG/B3,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global leader in discrete, logic, and PowerMOS semiconductors, spun off from NXP in 2017 and focused on automotive, industrial, computing, and consumer markets.

This part belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered to replace general-purpose transistors in digital logic interfacing, reducing design complexity and improving manufacturing yield.

FAQ

What is the maximum operating temperature for PUMD2/DG/B3,115?

The device supports junction temperatures up to 150 °C and ambient temperatures from −55 °C to +150 °C. Its thermal resistance is 417 K/W (per device) on standard FR4 PCB, meaning it dissipates 300 mW max at Tamb = 25 °C before reaching Tj = 150 °C. Derating begins linearly above 25 °C per Figure 1 in the datasheet.

Can PUMD2/DG/B3,115 be used in high-frequency switching applications?

Yes, but within limits: TR1 (NPN) has fT = 230 MHz and TR2 (PNP) has fT = 180 MHz at IC = 10 mA. Practical switching frequencies are constrained by input capacitance (Cc ≤ 2.5 pF for TR1, ≤3 pF for TR2) and VI(on)/VI(off) transition times. It is suitable for digital logic interfacing up to ~10 MHz, not RF or Class-D audio.

Is the pinout compatible with other SOT363 dual transistors like PMMD2?

No-PUMD2/DG/B3,115 uses a unique pin assignment: Pin 1 = TR1 emitter, Pin 2 = TR1 base, Pin 3 = TR2 collector, Pin 4 = TR2 emitter, Pin 5 = TR2 base, Pin 6 = TR1 collector. PMMD2 and similar parts use different internal connectivity (e.g., dual NPN or dual PNP), making them non-interchangeable without circuit redesign.

Does PUMD2/DG/B3,115 require external pull-up or pull-down resistors?

No-its integrated R1 and R2 bias resistors provide defined base termination. VI(off) is guaranteed ≤0.8 V and VI(on) ≥1.7 V, ensuring clean logic-level recognition without external components. However, if interfacing with open-drain outputs or floating sources, a weak external pull-up may be needed to ensure valid off-state voltage.