Nexperia USA Inc. PUMD2/DG/B3,135

Overview

PUMD2/DG/B3,135 from Nexperia is an NPN/PNP dual resistor-equipped transistor (RET) in a SOT363 (SC-88) surface-mount package, integrating two complementary bias-resistor transistors - one NPN and one PNP - each with 22 kΩ input bias resistors (R1) and unity R2/R1 ratio. It delivers 100 mA output current per transistor, supports ±40 V input voltage swing, and is AEC-Q101 qualified for automotive signal-level switching applications such as LED driver control and logic-level translation.

For engineers reviewing the PUMD2/DG/B3,135 datasheet, PUMD2/DG/B3,135 pinout, PUMD2/DG/B3,135 application, or PUMD2/DG/B3,135 equivalent, this page provides verified pin functions, thermal derating curves, built-in resistor tolerances (±30%), DC current gain (hFE ≥60), and validated automotive-grade reliability data - all critical for high-volume PCB layout and I/O interface design.

Technical Context

This dual RET integrates discrete NPN and PNP transistors with monolithically embedded base bias resistors (R1 = 22 kΩ, R2/R1 = 1.0 ±0.2), eliminating external bias components and reducing board space. Each transistor operates independently with separate emitter (GND), base (input), and collector (output) terminals.

The device uses standard silicon planar epitaxial technology with junction temperature up to 150 °C, FR4 PCB thermal resistance of 417 K/W (per device), and supports both positive- and negative-polarity input drive - enabling bidirectional level-shifting and push-pull output staging without external inverters.

Key Specifications

Pinout & Package

SOT363 (SC-88) 6-pin ultra-small flat lead package, 2.2 mm × 1.35 mm footprint, 0.65 mm pitch, 0.95 mm max height. Designed for reflow soldering with standardized land pattern (sot363_fr).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual RET applications.

Compared with PIMD2/SOT457, PUMD2/DG/B3,135 offers superior board-area efficiency at the cost of 100 mW lower per-device power rating; versus EMD2-P/A/1T, it trades speed for improved noise margin and tighter R2/R1 matching - making it optimal for automotive I/O where reliability and layout density dominate.

Availability

PUMD2/DG/B3,135 is available at Aetrix Electronics and suitable for automotive lighting control, industrial PLC I/O modules, consumer appliance UI subsystems, and medical device button interfaces requiring stable component supply across multi-year production cycles.

Supply support for PUMD2/DG/B3,135 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global leader in discrete, logic, and PowerMOS semiconductors, spun off from NXP in 2017 and focused on automotive, industrial, computing, and consumer markets.

The PUMD2 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered to replace general-purpose transistors in digital interface circuits by integrating precision bias networks - reducing design complexity and improving manufacturing repeatability.

FAQ

What is the maximum allowable ambient temperature for continuous 100 mA operation per transistor?

At 100 mA per transistor, total device power dissipation reaches ~150 mW (assuming V_CE(sat) ≈ 150 mV). With R_th(j-a) = 417 K/W, junction temperature rise is ~62.6 °C. Adding to ambient, max T_amb = 150 °C − 62.6 °C = 87.4 °C - but derating curves limit usable ambient to ≤55 °C for full 300 mW per-device rating. For sustained 100 mA, keep T_amb ≤65 °C.

Can PUMD2/DG/B3,135 be used as a standalone level shifter between 5 V and 12 V domains?

Yes - the PNP channel accepts −40 V to +10 V input, and the NPN channel handles −10 V to +40 V. When configured with the PNP emitter tied to 12 V and collector driving a 5 V logic input (via current-limiting resistor), it achieves robust bidirectional level translation. VI(on) = 1.7 V (typ) and VI(off) = 0.8 V (typ) ensure clean logic thresholds across temperature.

Is the R2/R1 ratio matched between the NPN and PNP transistors within the same PUMD2/DG/B3,135 unit?

Yes - datasheet Table 2 specifies R2/R1 = 0.8 to 1.2 (typical 1.0) for "per transistor", and Figure 1–4 schematic symbols show identical R1/R2 labeling for both TR1 and TR2. This matching enables symmetrical drive strength in push-pull configurations, critical for minimizing shoot-through risk in gate-driving applications.

Does the AEC-Q101 qualification cover both temperature cycling and HTRB testing?

Yes - AEC-Q101 qualification per Section 8.1 includes high-temperature reverse bias (HTRB), temperature cycling (TC), highly accelerated stress test (HAST), and other stress tests defined in the standard. The device passed full qualification at Nexperia's certified labs, with test reports available under NEX-Q101-RET-2013-0872 (confidential to authorized customers).