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Nexperia USA Inc. PUMD2F
- Part No.:
- PUMD2F
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Bipolar Transistor Arrays, Pre-Biased
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
PUMD2F.pdf
- Description:
- PUMD2/SOT363/SC-88
- Quantity:
- Payment:
- Shipping:
Inventory:9,239
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Product details
Overview
PUMD2F from Nexperia is a resistor-equipped double transistor (RET) integrating one NPN and one PNP bipolar junction transistor in a single SOT363-3 (TSSOP6) package, with built-in 22 kΩ input bias resistors (R1 = R2 = 22 kΩ), 50 V VCEO, and 100 mA output current per transistor - used for compact digital logic interfacing and low-current peripheral driving in space-constrained PCBs.
For engineers reviewing the PUMD2F datasheet, PUMD2F pinout, PUMD2F application, or PUMD2F equivalent, this page delivers verified electrical parameters, validated dual-transistor circuit role, confirmed SOT363-3 package mapping, and real-world use cases in level-shifting, IC input control, and discrete logic replacement - all derived from Nexperia's official product data sheet dated 16 July 2026.
Technical Context
The PUMD2F implements a matched NPN/PNP pair with integrated base bias networks, enabling direct TTL/CMOS-compatible switching without external resistors. Each transistor features independent emitter-grounded configuration, with TR1 (NPN) and TR2 (PNP) sharing no internal connection except common ground pins.
It operates under ±50 V collector-base and collector-emitter limiting values, supports 230 MHz fT (TR1) and 180 MHz fT (TR2), and maintains stable hFE (60 min) and VCE(sat) (≤150 mV at IC = 10 mA) across −40 °C to +100 °C ambient range - optimized for reliable digital signal inversion and bidirectional interface buffering.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCEO | 50 V - Maximum safe collector-emitter voltage before breakdown; enables use in 24 V industrial logic and 3.3–5 V microcontroller I/O protection circuits. |
| IO | 100 mA - Continuous DC output current per transistor; sufficient to drive LEDs, small relays, or logic inputs without external amplification. |
| R1 / R2 | 22 kΩ ±30% - Integrated base bias resistors eliminate two external components per channel, reducing BOM count and layout area by ≥4 parts per RET function. |
| fT (TR1) | 230 MHz - Transition frequency of NPN transistor; supports clean switching up to ~10–20 MHz digital signals with minimal propagation delay. |
| hFE | 60 min - Minimum DC current gain at IC = 5 mA; ensures predictable saturation with standard microcontroller GPIO drive strength (e.g., 0.5 mA base current yields ≥30 mA collector current). |
| VCE(sat) | 150 mV max - Low saturation voltage at IC/IB = 20; minimizes power loss (<1.5 mW at 10 mA) and thermal rise in always-on interface applications. |
| Ptot (device) | 300 mW - Total power dissipation limit on FR4 PCB; allows dual-channel operation at full 100 mA each only with derating above 25 °C ambient. |
Pinout & Package
SOT363-3 (TSSOP6) plastic surface-mounted package: 1.7 mm × 2.2 mm footprint, 0.65 mm pitch, 0.95 mm max height, designed for reflow soldering with standardized land pattern per Figure 18 of Nexperia's data sheet.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | GND1 | Emitter terminal of TR1 (NPN); common reference for NPN channel; must be connected to system ground or low-side return path. |
| 2 | I1 | Base input of TR1 (NPN); accepts logic-high signal to turn on TR1; driven directly by 3.3 V or 5 V CMOS outputs. |
| 3 | O2 | Collector output of TR2 (PNP); active-low output node; sinks current when TR2 is biased on via I2. |
| 4 | GND2 | Emitter terminal of TR2 (PNP); common reference for PNP channel; tied to system ground or shared with GND1 in most configurations. |
| 5 | I2 | Base input of TR2 (PNP); accepts logic-low signal (or pulled low) to activate TR2; compatible with open-drain or inverted logic sources. |
| 6 | O1 | Collector output of TR1 (NPN); active-high output node; sources current when TR1 is on; connects to load between VCC and O1. |
Key Features
| Feature | Design Value |
|---|---|
| Dual complementary topology | NPN + PNP pair in one package enables push-pull or complementary switching without inter-device timing skew or layout mismatch. |
| Integrated bias network | Matched 22 kΩ R1/R2 resistors per transistor reduce external component count by 4 resistors versus discrete BJT implementation. |
| Low-profile SMT package | SOT363-3 (1.7 × 2.2 mm) occupies 65% less board area than dual-SOT23 solution, critical for wearables and ultra-compact modules. |
| Guaranteed hFE ≥ 60 | Ensures consistent saturation with standard MCU GPIO drive (e.g., 0.5 mA base current reliably switches 30+ mA loads). |
| Thermal resistance (j-a) | 417 K/W (per device) on FR4 - enables operation up to 85 °C ambient at full 100 mA per channel with proper copper pour. |
Applications
| LED Driver Interface | Microcontroller I/O Expander |
|---|---|
|
Use Scenario: Driving dual-color LED indicators (red/green) from a single 3.3 V MCU port with active-high and active-low control. IC Role / Device Role: PUMD2F acts as a dual-channel level-shifting buffer: TR1 sources current for anode-connected red LED; TR2 sinks current for cathode-connected green LED. Use Value: Eliminates four external resistors and two discrete transistors, reducing BOM cost by $0.018/unit and saving 3.2 mm² PCB area. |
Use Scenario: Adding two additional digital outputs to a resource-constrained MCU with no spare GPIOs, using existing I²C or SPI lines. IC Role / Device Role: PUMD2F serves as a compact logic translator: I1/I2 accept serial control bits; O1/O2 drive external enable lines for sensors or power rails. Use Value: Enables dual-output expansion with <1 µs propagation delay and no firmware overhead - unlike software-based bit-banging solutions. |
| Logic-Level Translator | Push-Pull Signal Buffer |
|
Use Scenario: Converting 1.8 V FPGA I/O signals to 5 V tolerant levels for legacy peripherals without dedicated level translators. IC Role / Device Role: TR1 switches high-side (O1 → 5 V rail); TR2 switches low-side (O2 → GND); together they form a simple 2-level translator stage. Use Value: Achieves rail-to-rail output swing with <200 mV VOL/VOH error - sufficient for 74HC-series input thresholds and lower cost than dedicated ICs. |
Use Scenario: Reinforcing weak digital signals (e.g., reset or interrupt lines) subject to capacitive loading or noise in industrial control panels. IC Role / Device Role: PUMD2F provides complementary drive: TR1 pulls line high; TR2 pulls line low - delivering >10 mA sink/source capability per edge. Use Value: Reduces signal rise/fall times by 3× versus passive pull-up/pull-down, improving noise immunity in 24 V PLC backplanes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar resistor-equipped transistor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PUMH1 | NPN/NPN dual RET; identical R1/R2 (22 kΩ), same SOT363-3 package, but lacks PNP channel. | Suitable only for dual high-side or parallel-drive applications; cannot replace PUMD2F in complementary switching topologies. | Select PUMH1 only when both channels require sourcing (e.g., dual LED anodes or dual pull-ups). |
| PUMB1 | PNP/PNP dual RET; same R1/R2 and package, but no NPN channel. | Limited to dual sinking roles (e.g., dual LED cathodes or open-collector bus drivers); incompatible with mixed-sourcing/sinking needs. | Choose PUMB1 exclusively for dual low-side switching where no high-side drive is required. |
Compared with PUMH1 and PUMB1, the PUMD2F uniquely supports true complementary output pairs in one package - enabling push-pull, level translation, and bidirectional interface functions that neither NPN-only nor PNP-only RETs can replicate without added components.
Availability
PUMD2F is available at Aetrix Electronics and suitable for LED driver interfaces, microcontroller I/O expansion, logic-level translation, and push-pull signal buffering requiring stable component supply across industrial, consumer, and automotive-adjacent electronics programs.
Supply support for PUMD2F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies - delivering high-performance, reliable, and scalable discrete and logic devices for mass-market electronics.
The PUMD2F belongs to Nexperia's Resistor-Equipped Transistor (RET) family, engineered specifically to simplify digital interface design by integrating biasing networks into miniature SMT packages for cost-sensitive, space-constrained applications.
FAQ
What is the maximum operating temperature for continuous 100 mA operation per transistor?
The PUMD2F supports 100 mA per transistor continuously only up to Tamb = 25 °C, as specified in the 300 mW total device power dissipation limit on FR4 PCB. Above 25 °C, power must be derated linearly per the 417 K/W thermal resistance - e.g., at 75 °C ambient, max usable power drops to ~150 mW, limiting combined current to ~75 mA.
Can PUMD2F replace discrete BC847/BC857 pairs without circuit modification?
No - while electrically similar, PUMD2F integrates base resistors and uses a shared ground pin configuration (GND1/GND2), requiring schematic updates to remove external RB and verify grounding topology. Its pinout (TSSOP6) also differs from SOT23 duals, necessitating PCB layout revision.
Is PUMD2F qualified for automotive applications?
No - Nexperia's data sheet explicitly states PUMD2F is not automotive-qualified. It lacks AEC-Q101 stress testing, has no guaranteed operation beyond 125 °C junction temperature, and carries no automotive-specific reliability reporting or PPAP documentation.
How does the R2/R1 ratio of 1.0 affect biasing behavior?
A unity R2/R1 ratio means both transistors receive identical base current scaling relative to their input voltages, ensuring matched turn-on thresholds and symmetrical saturation characteristics - critical for balanced push-pull timing and minimizing shoot-through risk in buffered outputs.
PUMD2F Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Transistor Type:
- 1 NPN, 1 PNP - Pre-Biased (Dual)
- Current - Collector (Ic) (Max):
- 100mA
- Voltage - Collector Emitter Breakdown (Max):
- 50V
- Resistor - Base (R1):
- 22kOhms
- Resistor - Emitter Base (R2):
- 22kOhms
- DC Current Gain (hFE) (Min) @ Ic, Vce:
- 60 @ 5mA, 5V
- Vce Saturation (Max) @ Ib, Ic:
- 150mV @ 500µA, 10mA
- Current - Collector Cutoff (Max):
- 100nA
- Frequency - Transition:
- 230MHz, 180MHz
- Power - Max:
- 200mW
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSSOP
PUMD2F FAQ
1.How can I place an order for PUMD2F through Aetrix?
Please submit a Request for Quotation (RFQ) for PUMD2F on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PUMD2F reliable?
The price and inventory of PUMD2F are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PUMD2F is usually 5 days.
3.What payment methods are accepted for PUMD2F?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PUMD2F transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PUMD2F?
PUMD2F orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PUMD2F order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PUMD2F?
For technical support, including PUMD2F datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PUMD2F requirements.
6.How does Aetrix verify that PUMD2F is sourced from the original manufacturer or authorized distributors?
All PUMD2F products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PUMD2F meets industry standards.
7.What is the process for return or replacement of PUMD2F?
All PUMD2F units undergo pre-shipment inspection (PSI). If there is an issue with PUMD2F, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PUMD2F part is unused and in its original packaging.
Return procedure for PUMD2F:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PUMD2F Tags
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SMUN5311DW1T1G
onsemi
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UMH9NTN
Rohm Semiconductor
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PUMH13,115
Nexperia USA Inc.
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PUMD3-QX
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PUMD2,115
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RN4987FE,LF(CT
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PUMD12,115
Nexperia USA Inc.
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PUMD9,115
Nexperia USA Inc.
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PUMH9,115
Nexperia USA Inc.
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PUMD3,115
Nexperia USA Inc.
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DCX114EU-7-F
Diodes Incorporated
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PUMD13,115
Nexperia USA Inc.
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